39 	mxc_spi_regs_t *regs;  member
87 	mxc_spi_regs_t *regs = cfg->regs;  in spi_configure()  local
104 	ret = Wrap_MXC_SPI_Init(regs, master_mode, quad_mode, num_slaves, ss_polarity, spi_speed);  in spi_configure()
113 		ret = MXC_SPI_SetMode(regs, SPI_MODE_3);  in spi_configure()
115 		ret = MXC_SPI_SetMode(regs, SPI_MODE_2);  in spi_configure()
117 		ret = MXC_SPI_SetMode(regs, SPI_MODE_1);  in spi_configure()
119 		ret = MXC_SPI_SetMode(regs, SPI_MODE_0);  in spi_configure()
125 	ret = MXC_SPI_SetDataSize(regs, SPI_WORD_SIZE_GET(config->operation));  in spi_configure()
133 		ret = MXC_SPI_SetWidth(regs, SPI_WIDTH_QUAD);  in spi_configure()
136 		ret = MXC_SPI_SetWidth(regs, SPI_WIDTH_DUAL);  in spi_configure()
143 		ret = MXC_SPI_SetWidth(regs, SPI_WIDTH_STANDARD);  in spi_configure()
254 	MXC_SPI_ClearTXFIFO(cfg->regs);  in spi_max32_transceive()
310 	data->req.spi = cfg->regs;  in spi_max32_transceive()
315 	spi_max32_setup(cfg->regs, &data->req);  in spi_max32_transceive()
317 	MXC_SPI_SetTXThreshold(cfg->regs, 1);  in spi_max32_transceive()
319 		MXC_SPI_SetRXThreshold(cfg->regs, 2);  in spi_max32_transceive()
320 		MXC_SPI_EnableInt(cfg->regs, ADI_MAX32_SPI_INT_EN_RX_THD);  in spi_max32_transceive()
322 	MXC_SPI_EnableInt(cfg->regs, ADI_MAX32_SPI_INT_EN_TX_THD | ADI_MAX32_SPI_INT_EN_MST_DONE);  in spi_max32_transceive()
326 			MXC_SPI_WriteTXFIFO(cfg->regs, data->dummy, MIN(len, sizeof(data->dummy)));  in spi_max32_transceive()
328 		data->req.txCnt = MXC_SPI_WriteTXFIFO(cfg->regs, data->req.txData, len);  in spi_max32_transceive()
331 	MXC_SPI_StartTransmission(cfg->regs);  in spi_max32_transceive()
333 	ret = spi_max32_transceive_sync(cfg->regs, data, dfs_shift);  in spi_max32_transceive()
378 	MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl);  in transceive()
384 		cfg->regs->ctrl0 =  in transceive()
385 			(cfg->regs->ctrl0 & ~MXC_F_SPI_CTRL0_START) | MXC_F_SPI_CTRL0_SS_CTRL;  in transceive()
415 			cfg->regs->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL |  in transceive()
417 			cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN;  in transceive()
533 	mxc_spi_regs_t *spi = cfg->regs;  in transceive_dma()
566 	MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl);  in transceive_dma()
573 	MXC_SPI_SetSlave(cfg->regs, ctx->config->slave);  in transceive_dma()
668 	MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl);  in spi_max32_iodev_prepare_start()
674 		cfg->regs->ctrl0 = (cfg->regs->ctrl0 & ~MXC_F_SPI_CTRL0_START) |  in spi_max32_iodev_prepare_start()
694 			cfg->regs->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL |  in spi_max32_iodev_complete()
696 			cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN;  in spi_max32_iodev_complete()
796 	mxc_spi_regs_t *spi = cfg->regs;  in spi_max32_isr()
807 				req->txCnt += MXC_SPI_WriteTXFIFO(cfg->regs, data->dummy,  in spi_max32_isr()
858 	mxc_spi_regs_t *regs = cfg->regs;  in spi_max32_init()  local
865 	MXC_SPI_Shutdown(regs);  in spi_max32_init()
957 		.regs = (mxc_spi_regs_t *)DT_INST_REG_ADDR(_num),                                  \