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Searched refs:phase (Results 26 – 50 of 116) sorted by relevance

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/Zephyr-latest/include/zephyr/bluetooth/mesh/
Dcfg.h394 uint8_t bt_mesh_subnet_kr_phase_set(uint16_t net_idx, uint8_t *phase);
404 uint8_t bt_mesh_subnet_kr_phase_get(uint16_t net_idx, uint8_t *phase);
Ddfu_cli.h64 uint8_t phase; member
82 enum bt_mesh_dfu_phase phase; member
Dblob_srv.h140 enum bt_mesh_blob_xfer_phase phase; member
Ddfu_srv.h192 uint8_t phase; member
/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/
DKconfig8 SPI mode value (clock polarity and phase) used in the test.
/Zephyr-latest/drivers/clock_control/
DKconfig.litex13 such as phase, duty cycle, frequency for up to 7
Dclock_control_rpi_pico.c194 uint32_t phase; member
728 ret = rpi_pico_rosc_write(dev, &rosc_regs->phase, in clock_control_rpi_pico_init()
730 config->rosc_data.phase); in clock_control_rpi_pico_init()
937 .phase = (COND_CODE_1(DT_NODE_HAS_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc),
941 phase),
942 ((DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, rosc), phase) &
/Zephyr-latest/subsys/net/l2/ppp/
Dppp_l2.c180 if (ctx->phase != PPP_RUNNING && !net_pkt_is_ppp(pkt)) { in ppp_send()
247 if (ctx->phase == PPP_DEAD) { in ppp_lcp_close()
260 if (ctx->phase == PPP_DEAD) { in ppp_lcp_lower_down_async()
277 if (ctx->phase == PPP_DEAD) { in ppp_lcp_lower_down()
/Zephyr-latest/samples/sensor/qdec/boards/
Dmimxrt1050_evk_mimxrt1052_hyperflash.overlay30 /* disable to avoid encoder phase input conflict */
/Zephyr-latest/tests/bsim/bluetooth/mesh/src/
Dtest_blob.c964 ASSERT_TRUE(blob_srv.phase == BT_MESH_BLOB_XFER_PHASE_COMPLETE); in test_srv_trans_complete()
1069 ASSERT_TRUE(blob_srv.phase == BT_MESH_BLOB_XFER_PHASE_SUSPENDED); in test_srv_trans_resume()
1080 ASSERT_TRUE(blob_srv.phase == BT_MESH_BLOB_XFER_PHASE_COMPLETE); in test_srv_trans_resume()
1179 ASSERT_TRUE(blob_srv.phase == BT_MESH_BLOB_XFER_PHASE_COMPLETE); in test_srv_trans_persistency_pull()
1524 ASSERT_EQUAL(BT_MESH_BLOB_XFER_PHASE_SUSPENDED, blob_srv.phase); in srv_check_reboot_and_continue()
1554 ASSERT_EQUAL(BT_MESH_BLOB_XFER_PHASE_WAITING_FOR_START, blob_srv.phase); in test_srv_stop()
1557 ASSERT_EQUAL(BT_MESH_BLOB_XFER_PHASE_WAITING_FOR_START, blob_srv.phase); in test_srv_stop()
1563 ASSERT_EQUAL(BT_MESH_BLOB_XFER_PHASE_WAITING_FOR_BLOCK, blob_srv.phase); in test_srv_stop()
1570 ASSERT_EQUAL(expected_stop_phase, blob_srv.phase); in test_srv_stop()
1574 ASSERT_EQUAL(BT_MESH_BLOB_XFER_PHASE_INACTIVE, blob_srv.phase); in test_srv_stop()
[all …]
Dtest_brg.c1004 uint8_t phase; in set_krp_phase() local
1007 ASSERT_OK(bt_mesh_cfg_cli_krp_set(0, BRIDGE_ADDR, net_idx, transition, &status, &phase)); in set_krp_phase()
1008 if (status || (phase != (transition == 0x02 ? 0x02 : 0x00))) { in set_krp_phase()
1010 transition, phase); in set_krp_phase()
1014 ASSERT_OK(bt_mesh_cfg_cli_krp_set(0, addr, net_idx, transition, &status, &phase)); in set_krp_phase()
1015 if (status || (phase != (transition == 0x02 ? 0x02 : 0x00))) { in set_krp_phase()
1017 transition, phase); in set_krp_phase()
/Zephyr-latest/drivers/disk/nvme/
Dnvme_cmd.c428 if (qpair->num_intr_handler_calls == 0 && qpair->phase == 0) { in nvme_cmd_qpair_process_completion()
438 if (NVME_STATUS_GET_P(status) != qpair->phase) { in nvme_cmd_qpair_process_completion()
466 qpair->phase = !qpair->phase; in nvme_cmd_qpair_process_completion()
535 qpair->phase = 1; in nvme_cmd_qpair_reset()
/Zephyr-latest/cmake/toolchain/xt-clang/
Dgeneric.cmake15 # lengthens the CMake phase of build, especially when xt-clang needs to
/Zephyr-latest/boards/phytec/reel_board/
Dreel_board_nrf52840_2.overlay61 * 2 bits represent the voltage in a phase:
72 * TPnx determines the length of each phase,
/Zephyr-latest/subsys/net/lib/shell/
Dppp.c78 PR("PPP phase : %s (%d)\n", ppp_phase_str(ctx->phase), in cmd_net_ppp_status()
79 ctx->phase); in cmd_net_ppp_status()
/Zephyr-latest/cmake/toolchain/xcc/
Dgeneric.cmake20 # lengthens the CMake phase of build, especially when XCC needs to
/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcxw_utils.c348 void set_csl_ie(uint8_t *pdu, uint16_t length, uint16_t period, uint16_t phase) in set_csl_ie() argument
353 sys_put_le16(phase, csl_ie_content); in set_csl_ie()
/Zephyr-latest/tests/drivers/can/timing/
DKconfig24 CiA 601-2 lists the following exemplary CAN FD data phase bitrates:
/Zephyr-latest/doc/project/
Drelease_process.rst23 - Each release period will consist of a development phase followed by a
24 stabilization phase. Release candidates will be tagged during the
25 stabilization phase. During the stabilization phase, only stabilization
29 - Development phase: all changes are considered and merged, subject to
31 - Stabilisation phase: the release manager creates a vN-rc1 tag and the tree
32 enters the stabilization phase
64 The development phase lasts for approximately three months. At the end of this time,
65 the release owner will declare that the development phase is over and releases the first
67 3.1.0, for example, the release which happens at the end of the development phase
81 rule, if you miss submitting your code during the development phase for a given
/Zephyr-latest/scripts/pylib/twister/twisterlib/
Dharness.py794 def get_testcase(self, tc_name, phase, ts_name=None): argument
814 if self.started_suites[ts_name_]['count'] < (0 if phase == 'TS_SUM' else 1):
828 def start_suite(self, suite_name, phase='TS_START'): argument
848 def end_suite(self, suite_name, phase='TS_END', suite_status=None): argument
850 if phase == 'TS_SUM' and self.started_suites[suite_name]['count'] == 0:
860 self.start_suite(suite_name, phase) # register skipped suites at their summary end
865 def start_case(self, tc_name, phase='TC_START'): argument
874 def end_case(self, tc_name, phase='TC_END'): argument
876 if phase == 'TS_SUM' and self.started_cases[tc_name]['count'] == 0:
885 elif phase != 'TS_SUM':
/Zephyr-latest/boards/silabs/dev_kits/sltb010a/
Dsltb010a.dts49 dpll-lock = "phase";
/Zephyr-latest/subsys/bluetooth/mesh/shell/
Ddfd.c29 srv->phase); in print_dfd_status()
31 if (srv->phase != BT_MESH_DFD_PHASE_IDLE && srv->dfu.xfer.slot) { in print_dfd_status()
170 "\"img_idx\": %d }%s", i + first, t->blob.addr, t->phase, t->status, in cmd_dfd_receivers_get()
/Zephyr-latest/drivers/spi/
Dspi_mcux_flexio.c163 if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { in spi_flexio_master_init()
184 if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) { in spi_flexio_master_init()
275 master_config.phase = in spi_mcux_flexio_configure()
/Zephyr-latest/drivers/can/
DKconfig34 int "Default CAN data phase bitrate"
38 Default initial CAN data phase bitrate in bits/s. This can be overridden per CAN controller
/Zephyr-latest/boards/silabs/dev_kits/xg27_dk2602a/
Dxg27_dk2602a.dts53 dpll-lock = "phase";

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