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/Zephyr-latest/soc/gaisler/gr716a/
Dlinker.ld15 * GR716A memory map
17 * LENGTH values represent the maximum possible. All memory regions may not be
/Zephyr-latest/boards/nxp/mimxrt1180_evk/
Dmimxrt1180_evk_mimxrt1189_cm33.dts29 hyperram0: memory@14000000 {
31 device_type = "memory";
/Zephyr-latest/samples/drivers/i2s/i2s_codec/
DREADME.rst11 an audio stream. It configures and starts from memory buffer or from DMIC to
33 from DMIC or from memory buffer.
/Zephyr-latest/dts/arm/atmel/
Dsam4l.dtsi40 sram0: memory@20000000 {
46 * memory available. The PicoCache will be keep disable to ensures
47 * deterministic behaviour. That way the extra memory can be
50 sram1: memory@21000000 {
51 compatible = "zephyr,memory-region", "mmio-sram";
53 zephyr,memory-region = "SRAM1";
/Zephyr-latest/boards/st/stm32f7508_dk/
Dstm32f7508_dk.dts11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
53 compatible = "zephyr,memory-region", "mmio-sram";
54 device_type = "memory";
56 zephyr,memory-region = "SDRAM1";
57 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
/Zephyr-latest/samples/drivers/ipm/ipm_ivshmem/
DREADME.rst5 Implement inter-processor mailbox (IPM) over IVSHMEM (Inter-VM shared memory)
30 shared memory size are decided at run-time (when the server is executed).
31 For Zephyr, the number of vectors and shared memory size of ivshmem are
101 Shared memory: 0xafa00000 of size 4194304 bytes
117 Shared memory: 0xafa00000 of size 4194304 bytes
129 Shared memory: 0xafa00000 of size 4194304 bytes
/Zephyr-latest/tests/drivers/dma/chan_blen_transfer/boards/
Dstm32f746g_disco.overlay12 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
/Zephyr-latest/tests/drivers/dma/loop_transfer/boards/
Dstm32f746g_disco.overlay12 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
/Zephyr-latest/soc/intel/intel_ish/intel_ish5/
Dlinker.ld7 #include <zephyr/arch/x86/memory.ld>
/Zephyr-latest/lib/hash/
DKconfig.hash_map23 large contiguous memory regions are scarce.
34 memory region.
38 memory caching.
/Zephyr-latest/tests/drivers/spi/spi_error_cases/boards/
Dnrf54h20dk_nrf54h20_cpuapp_fast.overlay60 memory-regions = <&dma_fast_region>;
76 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay52 memory-regions = <&cpuapp_dma_region>;
69 memory-regions = <&cpuapp_dma_region>;
/Zephyr-latest/doc/services/portability/
Dcmsis_rtos_v2.rst59 ``osErrorResource`` (the memory pool specified by
60 parameter mp_id is in an invalid memory pool state) is
64 ``osErrorResource`` (the memory pool specified by
65 parameter mp_id is in an invalid memory pool state) is
/Zephyr-latest/soc/intel/lakemont/
Dlinker.ld7 #include <zephyr/arch/x86/memory.ld>
/Zephyr-latest/dts/riscv/ite/
Dit81302dx.dtsi11 sram0: memory@80100000 {
Dit81202cx.dtsi11 sram0: memory@80100000 {
Dit81302cx.dtsi11 sram0: memory@80100000 {
Dit81202dx.dtsi11 sram0: memory@80100000 {
/Zephyr-latest/drivers/xen/
DCMakeLists.txt7 zephyr_sources(memory.c)
/Zephyr-latest/drivers/spi/
DKconfig.grlib_spimctrl5 bool "GRLIB SPI memory controller"
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc11u66.dtsi11 sram0: memory@10000000 {
Dnxp_lpc11u68.dtsi11 sram0: memory@10000000 {
Dnxp_lpc11u67.dtsi11 sram0: memory@10000000 {
/Zephyr-latest/doc/kernel/memory_management/
Dindex.rst6 The following contains various topics regarding memory management.
/Zephyr-latest/samples/subsys/mgmt/mcumgr/smp_svr/boards/
Dnrf52840dk_nrf52840_ram_load.overlay12 sram0: memory@20006000 {

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