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/Zephyr-latest/samples/subsys/ipc/rpmsg_service/boards/
Dmps2_an521_cpu0.overlay10 * shared memory reserved for the inter-processor communication
16 sramx: memory@281F8000 {
/Zephyr-latest/samples/subsys/ipc/rpmsg_service/remote/boards/
Dv2m_musca_b1_musca_b1_ns.overlay10 * shared memory reserved for the inter-processor communication
16 sramx: memory@20060000 {
Dmps2_an521_cpu1.overlay10 * shared memory reserved for the inter-processor communication
16 sramx: memory@281F8000 {
/Zephyr-latest/drivers/display/
DKconfig.ls0xx5 bool "LS0XX memory display controller driver"
10 Enable driver for sharp memory display series LS0XXX7DXXX
/Zephyr-latest/modules/lvgl/
DKconfig.memory35 Use a dedicated memory pool from a private sys heap.
44 Size of the memory pool in bytes
47 bool "Link memory pool to custom section"
50 Place LVGL memory pool in custom section, with tag ".lvgl_heap".
52 memory pool to a custom location, such as tightly coupled or
53 external memory.
74 controllers that require a framebuffer to be present in system memory,
84 so buffer must be aligned to prevent unaligned memory access
93 external memory.
/Zephyr-latest/dts/arm/st/u0/
Dstm32u073X8.dtsi11 sram1: memory@20000000 {
15 sram2: memory@20008000 {
Dstm32u073Xc.dtsi11 sram1: memory@20000000 {
15 sram2: memory@20008000 {
Dstm32u073Xb.dtsi11 sram1: memory@20000000 {
15 sram2: memory@20008000 {
/Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/snippets/
Dnxp-openamp-imx8-adsp.overlay10 * shared memory reserved for the inter-processor communication
16 dspsram3: memory@942f0000 {
/Zephyr-latest/boards/st/stm32f769i_disco/
Dstm32f769i_disco.dts10 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
29 compatible = "zephyr,memory-region", "mmio-sram";
30 device_type = "memory";
32 zephyr,memory-region = "SDRAM1";
33 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
78 quadspi_memory_avail: memory-avail@90000000 {
79 compatible = "zephyr,memory-region", "mmio-sram";
81 zephyr,memory-region = "QSPI_AVAIL";
82 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
/Zephyr-latest/subsys/ipc/ipc_service/backends/
DKconfig.rpmsg16 bool "Reset shared memory state"
18 Some platforms retain the memory content upon reset. This is
19 problematic because the backend expects a zero-ed memory to be
22 memory is reset on kernel initialization.
/Zephyr-latest/drivers/dma/
DKconfig.nxp_sof_host_dma14 memory and firmware (local) memory, which
21 int "Alignment (in bytes) required for memory regions passed to this driver"
26 this driver to adjust a memory region's size
/Zephyr-latest/snippets/nordic-flpr-xip/soc/
Dnrf54l15_cpuapp.overlay8 reserved-memory {
24 execution-memory = <&cpuflpr_code_partition>;
/Zephyr-latest/boards/panasonic/pan1783/
Dpre_dt_board.cmake7 # - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
/Zephyr-latest/dts/arm/st/l4/
Dstm32l471Xg.dtsi11 sram0: memory@20000000 {
14 sram1: memory@10000000 {
Dstm32l475Xe.dtsi10 sram0: memory@20000000 {
13 sram1: memory@10000000 {
Dstm32l486Xg.dtsi11 sram0: memory@20000000 {
14 sram1: memory@10000000 {
Dstm32l496Xg.dtsi10 sram0: memory@20000000 {
13 sram1: memory@10000000 {
Dstm32l4a6Xg.dtsi11 sram0: memory@20000000 {
14 sram1: memory@10000000 {
Dstm32l475Xg.dtsi10 sram0: memory@20000000 {
13 sram1: memory@10000000 {
Dstm32l476Xg.dtsi10 sram0: memory@20000000 {
13 sram1: memory@10000000 {
/Zephyr-latest/boards/nxp/imx93_evk/
Dimx93_evk_mimx9352_m33_ddr.dts19 ddr: memory@84000000 {
20 device_type = "memory";
/Zephyr-latest/boards/nxp/imx95_evk/
Dimx95_evk_mimx9596_m7_ddr.dts19 ddr: memory@80000000 {
20 device_type = "memory";
/Zephyr-latest/samples/subsys/ipc/openamp_rsc_table/boards/
Dimx8mp_evk_mimx8ml8_adsp.overlay10 * shared memory reserved for the inter-processor communication
16 dspsram3: memory@942f0000 {
/Zephyr-latest/drivers/memc/
DKconfig.smartbond7 bool "Smartbond NOR/PSRAM memory controller"
11 Enable Smartbond NOR/PSRAM memory controller.

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