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/Zephyr-latest/drivers/lora/
Dhal_common.c107 void BoardCriticalSectionBegin(uint32_t *mask) in BoardCriticalSectionBegin() argument
109 *mask = irq_lock(); in BoardCriticalSectionBegin()
112 void BoardCriticalSectionEnd(uint32_t *mask) in BoardCriticalSectionEnd() argument
114 irq_unlock(*mask); in BoardCriticalSectionEnd()
/Zephyr-latest/drivers/gpio/
Dgpio_ifx_cat1.c111 uint32_t mask, uint32_t value) in gpio_cat1_port_set_masked_raw() argument
116 GPIO_PRT_OUT(base) = (GPIO_PRT_OUT(base) & ~mask) | (mask & value); in gpio_cat1_port_set_masked_raw()
122 uint32_t mask) in gpio_cat1_port_set_bits_raw() argument
127 GPIO_PRT_OUT_SET(base) = mask; in gpio_cat1_port_set_bits_raw()
133 uint32_t mask) in gpio_cat1_port_clear_bits_raw() argument
138 GPIO_PRT_OUT_CLR(base) = mask; in gpio_cat1_port_clear_bits_raw()
144 uint32_t mask) in gpio_cat1_port_toggle_bits() argument
149 GPIO_PRT_OUT_INV(base) = mask; in gpio_cat1_port_toggle_bits()
Dgpio_iproc.c73 static int gpio_iproc_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) in gpio_iproc_port_set_masked_raw() argument
79 value = (value & (~mask)) | (value & mask); in gpio_iproc_port_set_masked_raw()
85 static int gpio_iproc_port_set_bits_raw(const struct device *dev, uint32_t mask) in gpio_iproc_port_set_bits_raw() argument
90 sys_write32(mask, base + IPROC_GPIO_DATA_OUT_OFFSET); in gpio_iproc_port_set_bits_raw()
95 static int gpio_iproc_port_clear_bits_raw(const struct device *dev, uint32_t mask) in gpio_iproc_port_clear_bits_raw() argument
103 value = (value & ~mask); in gpio_iproc_port_clear_bits_raw()
109 static int gpio_iproc_port_toggle_bits(const struct device *dev, uint32_t mask) in gpio_iproc_port_toggle_bits() argument
117 value = (value ^ mask); in gpio_iproc_port_toggle_bits()
Dgpio_mcux.c41 uint32_t mask = 0U; in gpio_mcux_configure() local
81 mask |= PORT_PCR_MUX_MASK; in gpio_mcux_configure()
92 mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; in gpio_mcux_configure()
110 mask |= PORT_PCR_DSE_MASK; in gpio_mcux_configure()
122 port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; in gpio_mcux_configure()
138 uint32_t mask, in gpio_mcux_port_set_masked_raw() argument
144 gpio_base->PDOR = (gpio_base->PDOR & ~mask) | (mask & value); in gpio_mcux_port_set_masked_raw()
150 uint32_t mask) in gpio_mcux_port_set_bits_raw() argument
155 gpio_base->PSOR = mask; in gpio_mcux_port_set_bits_raw()
161 uint32_t mask) in gpio_mcux_port_clear_bits_raw() argument
[all …]
Dgpio_ite_it8xxx2_v2.c86 uint8_t mask = BIT(pin); in gpio_ite_configure() local
123 ECREG(reg_gpotr) |= mask; in gpio_ite_configure()
125 ECREG(reg_gpotr) &= ~mask; in gpio_ite_configure()
135 ECREG(reg_p18scr) |= mask; in gpio_ite_configure()
136 data->volt_default_set &= ~mask; in gpio_ite_configure()
138 ECREG(reg_p18scr) &= ~mask; in gpio_ite_configure()
144 data->volt_default_set &= ~mask; in gpio_ite_configure()
146 ECREG(reg_p18scr) &= ~mask; in gpio_ite_configure()
147 data->volt_default_set |= mask; in gpio_ite_configure()
157 ECREG(reg_gpdr) |= mask; in gpio_ite_configure()
[all …]
Dgpio_stellaris.c39 #define GPIO_RW_MASK_ADDR(base, offset, mask) \ argument
40 (GPIO_REG_ADDR(base, offset) | (mask << 2))
150 uint32_t mask, in gpio_stellaris_port_set_masked_raw() argument
156 sys_write32(value, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask)); in gpio_stellaris_port_set_masked_raw()
162 uint32_t mask) in gpio_stellaris_port_set_bits_raw() argument
167 sys_write32(mask, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask)); in gpio_stellaris_port_set_bits_raw()
173 uint32_t mask) in gpio_stellaris_port_clear_bits_raw() argument
178 sys_write32(0, GPIO_RW_MASK_ADDR(base, GPIO_DATA_OFFSET, mask)); in gpio_stellaris_port_clear_bits_raw()
184 uint32_t mask) in gpio_stellaris_port_toggle_bits() argument
191 value ^= mask; in gpio_stellaris_port_toggle_bits()
Dgpio_psoc6.c105 uint32_t mask, in gpio_psoc6_port_set_masked_raw() argument
111 GPIO_PRT_OUT(port) = (GPIO_PRT_IN(port) & ~mask) | (mask & value); in gpio_psoc6_port_set_masked_raw()
117 uint32_t mask) in gpio_psoc6_port_set_bits_raw() argument
122 GPIO_PRT_OUT_SET(port) = mask; in gpio_psoc6_port_set_bits_raw()
128 uint32_t mask) in gpio_psoc6_port_clear_bits_raw() argument
133 GPIO_PRT_OUT_CLR(port) = mask; in gpio_psoc6_port_clear_bits_raw()
139 uint32_t mask) in gpio_psoc6_port_toggle_bits() argument
144 GPIO_PRT_OUT_INV(port) = mask; in gpio_psoc6_port_toggle_bits()
Dgpio_stmpe1600.c202 uint32_t mask, uint32_t value) in stmpe1600_port_set_masked_raw() argument
213 GPSR = (drvdata->GPSR & ~mask) | (mask & value); in stmpe1600_port_set_masked_raw()
223 static int stmpe1600_port_set_bits_raw(const struct device *dev, uint32_t mask) in stmpe1600_port_set_bits_raw() argument
225 return stmpe1600_port_set_masked_raw(dev, mask, mask); in stmpe1600_port_set_bits_raw()
228 static int stmpe1600_port_clear_bits_raw(const struct device *dev, uint32_t mask) in stmpe1600_port_clear_bits_raw() argument
230 return stmpe1600_port_set_masked_raw(dev, mask, 0); in stmpe1600_port_clear_bits_raw()
233 static int stmpe1600_port_toggle_bits(const struct device *dev, uint32_t mask) in stmpe1600_port_toggle_bits() argument
243 GPSR = drvdata->GPSR ^ mask; in stmpe1600_port_toggle_bits()
Dgpio_b91.c226 uint8_t mask; in gpio_b91_up_down_res_set() local
235 mask = 0xfc; in gpio_b91_up_down_res_set()
238 mask = 0xf3; in gpio_b91_up_down_res_set()
241 mask = 0xcf; in gpio_b91_up_down_res_set()
244 mask = 0x3f; in gpio_b91_up_down_res_set()
249 analog_write_reg8(analog_reg, (analog_read_reg8(analog_reg) & mask) | val); in gpio_b91_up_down_res_set()
361 gpio_port_pins_t mask, in gpio_b91_port_set_masked_raw() argument
366 gpio->output = (gpio->output & ~mask) | (value & mask); in gpio_b91_port_set_masked_raw()
373 gpio_port_pins_t mask) in gpio_b91_port_set_bits_raw() argument
377 gpio->output |= mask; in gpio_b91_port_set_bits_raw()
[all …]
Dgpio_altera_pio.c123 static int gpio_altera_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask) in gpio_altera_port_set_bits_raw() argument
133 if ((port_pin_mask & mask) == 0) { in gpio_altera_port_set_bits_raw()
137 if (!gpio_pin_direction(dev, mask)) { in gpio_altera_port_set_bits_raw()
145 sys_write32(mask, addr); in gpio_altera_port_set_bits_raw()
148 sys_set_bits(addr, mask); in gpio_altera_port_set_bits_raw()
156 static int gpio_altera_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask) in gpio_altera_port_clear_bits_raw() argument
167 if ((port_pin_mask & mask) == 0) { in gpio_altera_port_clear_bits_raw()
171 if (!gpio_pin_direction(dev, mask)) { in gpio_altera_port_clear_bits_raw()
179 sys_write32(mask, addr); in gpio_altera_port_clear_bits_raw()
182 sys_clear_bits(addr, mask); in gpio_altera_port_clear_bits_raw()
/Zephyr-latest/drivers/rtc/
Drtc_mc146818.c268 static bool rtc_mc146818_validate_alarm(const struct rtc_time *timeptr, uint32_t mask) in rtc_mc146818_validate_alarm() argument
270 if ((mask & RTC_ALARM_TIME_MASK_SECOND) && in rtc_mc146818_validate_alarm()
275 if ((mask & RTC_ALARM_TIME_MASK_MINUTE) && in rtc_mc146818_validate_alarm()
280 if ((mask & RTC_ALARM_TIME_MASK_HOUR) && in rtc_mc146818_validate_alarm()
289 uint16_t *mask) in rtc_mc146818_alarm_get_supported_fields() argument
297 (*mask) = (RTC_ALARM_TIME_MASK_SECOND in rtc_mc146818_alarm_get_supported_fields()
304 static int rtc_mc146818_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in rtc_mc146818_alarm_set_time() argument
317 if ((mask > 0) && (timeptr == NULL)) { in rtc_mc146818_alarm_set_time()
323 if (!rtc_mc146818_validate_alarm(timeptr, mask)) { in rtc_mc146818_alarm_set_time()
328 if (mask & RTC_ALARM_TIME_MASK_SECOND) { in rtc_mc146818_alarm_set_time()
[all …]
Drtc_ambiq.c177 uint16_t id, uint16_t *mask) in ambiq_rtc_alarm_get_supported_fields() argument
186 *mask = AMBIQ_RTC_ALARM_TIME_MASK; in ambiq_rtc_alarm_get_supported_fields()
192 static int ambiq_rtc_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, in ambiq_rtc_alarm_get_time() argument
213 *mask = data->alarm_set_mask; in ambiq_rtc_alarm_get_time()
217 timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec, *mask); in ambiq_rtc_alarm_get_time()
224 static int ambiq_rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in ambiq_rtc_alarm_set_time() argument
236 if (rtc_utils_validate_rtc_time(timeptr, mask) == false) { in ambiq_rtc_alarm_set_time()
243 if (mask & ~mask_available) { in ambiq_rtc_alarm_set_time()
247 data->alarm_set_mask = mask; in ambiq_rtc_alarm_set_time()
261 if (mask == 0) { in ambiq_rtc_alarm_set_time()
[all …]
/Zephyr-latest/tests/arch/arm/arm_sw_vector_relay/src/
Darm_sw_vector_relay.c46 uint32_t mask = MAX(128, Z_POW2_CEIL(4 * (16 + CONFIG_NUM_IRQS))) - 1; in ZTEST() local
48 zassert_true(((vector_table_addr) & mask) == 0, in ZTEST()
51 zassert_true(((vector_relay_table_addr) & mask) == 0, in ZTEST()
/Zephyr-latest/drivers/dai/nxp/esai/
Desai.h96 #define _ESAI_RX_FIFO_USAGE_EN(mask)\ argument
97 (((mask) << ESAI_RFCR_RE0_SHIFT) &\
101 #define _ESAI_TX_FIFO_USAGE_EN(mask)\ argument
102 (((mask) << ESAI_TFCR_TE0_SHIFT) &\
112 #define ESAI_TX_RX_FIFO_USAGE_EN(dir, mask)\ argument
113 ((dir) == DAI_DIR_TX ? _ESAI_TX_FIFO_USAGE_EN(mask) :\
114 _ESAI_RX_FIFO_USAGE_EN(mask))
116 #define _ESAI_TX_EN(mask)\ argument
117 (((mask) << ESAI_TCR_TE0_SHIFT) &\
121 #define _ESAI_RX_EN(mask)\ argument
[all …]
/Zephyr-latest/include/zephyr/arch/xtensa/
Dirq.h25 static inline void z_xt_ints_on(unsigned int mask) in z_xt_ints_on() argument
30 val |= mask; in z_xt_ints_on()
40 static inline void z_xt_ints_off(unsigned int mask) in z_xt_ints_off() argument
45 val &= ~mask; in z_xt_ints_off()
/Zephyr-latest/drivers/wifi/simplelink/
Dsimplelink.c40 uint8_t mask; member
71 simplelink_data.mask &= ~SIMPLELINK_IPV4; in simplelink_wifi_cb()
72 if ((simplelink_data.mask == 0) && in simplelink_wifi_cb()
80 simplelink_data.mask &= ~SIMPLELINK_IPV6; in simplelink_wifi_cb()
81 if ((simplelink_data.mask == 0) && in simplelink_wifi_cb()
224 simplelink_data.mask = 0; in simplelink_iface_init()
226 simplelink_data.mask |= IS_ENABLED(CONFIG_NET_IPV4) ? in simplelink_iface_init()
228 simplelink_data.mask |= IS_ENABLED(CONFIG_NET_IPV6) ? in simplelink_iface_init()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c136 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_set_priority() local
143 sys_write32(mask, ICENABLER(base, idx)); in arm_gic_irq_set_priority()
171 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_enable() local
185 sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx)); in arm_gic_irq_enable()
196 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_disable() local
199 sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx)); in arm_gic_irq_disable()
211 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_is_enabled() local
217 return (val & mask) != 0; in arm_gic_irq_is_enabled()
222 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_is_pending() local
228 return (val & mask) != 0; in arm_gic_irq_is_pending()
[all …]
/Zephyr-latest/drivers/serial/
Duart_mcux_iuart.c139 uint32_t mask = kUART_TxEmptyEnable; in mcux_iuart_irq_tx_ready() local
141 return (UART_GetEnabledInterrupts(config->base) & mask) in mcux_iuart_irq_tx_ready()
148 uint32_t mask = kUART_RxDataReadyEnable; in mcux_iuart_irq_rx_enable() local
150 UART_EnableInterrupts(config->base, mask); in mcux_iuart_irq_rx_enable()
156 uint32_t mask = kUART_RxDataReadyEnable; in mcux_iuart_irq_rx_disable() local
158 UART_DisableInterrupts(config->base, mask); in mcux_iuart_irq_rx_disable()
171 uint32_t mask = kUART_RxDataReadyEnable; in mcux_iuart_irq_rx_pending() local
173 return (UART_GetEnabledInterrupts(config->base) & mask) in mcux_iuart_irq_rx_pending()
180 uint32_t mask = kUART_RxOverrunEnable | kUART_ParityErrorEnable | in mcux_iuart_irq_err_enable() local
183 UART_EnableInterrupts(config->base, mask); in mcux_iuart_irq_err_enable()
[all …]
/Zephyr-latest/drivers/input/
Dinput_npcx_kbd.c78 uint32_t mask; in npcx_kbd_drive_column() local
87 mask = ~0; in npcx_kbd_drive_column()
90 mask = ~BIT_MASK(common->col_size); in npcx_kbd_drive_column()
96 mask = ~BIT(col); in npcx_kbd_drive_column()
99 LOG_DBG("Drive col mask: %x", mask); in npcx_kbd_drive_column()
101 inst->KBSOUT0 = (mask & 0xFFFF); in npcx_kbd_drive_column()
102 inst->KBSOUT1 = ((mask >> 16) & 0x03); in npcx_kbd_drive_column()
/Zephyr-latest/include/zephyr/sys/
Dutil_macro.h103 #define FIELD_GET(mask, value) (((value) & (mask)) / LSB_GET(mask)) argument
110 #define FIELD_PREP(mask, value) (((value) * LSB_GET(mask)) & (mask)) argument
Dspeculation.h46 uint32_t mask = ((signed_index - signed_array_size) & ~signed_index) >> 31; in k_array_index_sanitize() local
48 return index & mask; in k_array_index_sanitize()
/Zephyr-latest/lib/posix/options/
Dsyslog.c71 uint8_t mask = 0; in vsyslog() local
80 mask = syslog_mask; in vsyslog()
83 if ((BIT(level) & mask) == 0) { in vsyslog()
/Zephyr-latest/kernel/
Dcpu_mask.c69 uint32_t mask = BIT(cpu); in k_thread_cpu_pin() local
71 return cpu_mask_mod(thread, mask, ~mask); in k_thread_cpu_pin()
/Zephyr-latest/drivers/sensor/apds9306/
Dapds9306.c139 uint8_t mask; in apds9306_attr_set() local
149 mask = GENMASK(2, 0); in apds9306_attr_set()
153 mask = GENMASK(2, 0); in apds9306_attr_set()
157 mask = GENMASK(7, 4); in apds9306_attr_set()
163 if (i2c_reg_update_byte_dt(&config->i2c, reg, mask, temp)) { in apds9306_attr_set()
174 uint8_t mask; in apds9306_attr_get() local
185 mask = 0x00; in apds9306_attr_get()
188 mask = 0x00; in apds9306_attr_get()
191 mask = 0x04; in apds9306_attr_get()
201 value->val1 = (temp >> mask) & 0x07; in apds9306_attr_get()
/Zephyr-latest/include/zephyr/arch/common/
Dsys_bitops.h45 static ALWAYS_INLINE void sys_set_bits(mem_addr_t addr, unsigned int mask) in sys_set_bits() argument
49 *(volatile uint32_t *)addr = temp | mask; in sys_set_bits()
52 static ALWAYS_INLINE void sys_clear_bits(mem_addr_t addr, unsigned int mask) in sys_clear_bits() argument
56 *(volatile uint32_t *)addr = temp & ~mask; in sys_clear_bits()

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