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/Zephyr-latest/include/zephyr/sys/
Dspsc_lockfree.h73 const unsigned long mask; member
90 .mask = sz - 1, \
124 #define spsc_size(spsc) ((spsc)->_spsc.mask + 1)
133 #define z_spsc_mask(spsc, i) ((i) & (spsc)->_spsc.mask)
/Zephyr-latest/tests/net/socket/can/src/
Dmain.c109 expected.mask = 1234U; in ZTEST()
119 zassert_equal(zfilter.mask, expected.mask, "id mask not set"); in ZTEST()
139 zfilter.mask = 1234U; in ZTEST()
/Zephyr-latest/drivers/rtc/
Drtc_utils.h26 bool rtc_utils_validate_rtc_time(const struct rtc_time *timeptr, uint16_t mask);
Drtc_am1805.c319 static int am1805_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, in am1805_alarm_get_time() argument
348 *mask = (AM1805_RTC_ALARM_TIME_MASK); in am1805_alarm_get_time()
352 timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec, *mask); in am1805_alarm_get_time()
360 static int am1805_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in am1805_alarm_set_time() argument
374 if ((mask & ~(AM1805_RTC_ALARM_TIME_MASK)) != 0U) { in am1805_alarm_set_time()
375 LOG_ERR("unsupported alarm field mask 0x%04x", mask); in am1805_alarm_set_time()
403 if (mask == 0) { in am1805_alarm_set_time()
418 timeptr->tm_mon, timeptr->tm_wday, mask); in am1805_alarm_set_time()
442 static int am1805_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask) in am1805_alarm_get_supported_fields() argument
451 *mask = AM1805_RTC_ALARM_TIME_MASK; in am1805_alarm_get_supported_fields()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_eirq_nxp_s32.c65 uint32_t mask = GENMASK(CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_GROUP - 1, 0); in eirq_nxp_s32_interrupt_handler() local
70 pending &= mask << (irq_idx * CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_GROUP); in eirq_nxp_s32_interrupt_handler()
73 mask = LSB_GET(pending); in eirq_nxp_s32_interrupt_handler()
74 irq = u64_count_trailing_zeros(mask); in eirq_nxp_s32_interrupt_handler()
77 REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | mask); in eirq_nxp_s32_interrupt_handler()
83 pending ^= mask; in eirq_nxp_s32_interrupt_handler()
/Zephyr-latest/subsys/net/lib/sockets/
Dsockets_net_mgmt.c34 uint32_t mask; member
112 mgmt->mask = nm_addr->nm_mask; in znet_mgmt_bind()
115 mgmt->mask |= NET_MGMT_IFACE_BIT; in znet_mgmt_bind()
162 ret = net_mgmt_event_wait(mgmt->mask, &raised_event, in znet_mgmt_recvfrom()
167 mgmt->mask, in znet_mgmt_recvfrom()
185 if ((mgmt->mask & raised_event) != raised_event) { in znet_mgmt_recvfrom()
/Zephyr-latest/drivers/gpio/
Dgpio_mcux_lpc.c186 uint32_t mask, in gpio_mcux_lpc_port_set_masked_raw() argument
194 gpio_base->MASK[port] = ~mask; in gpio_mcux_lpc_port_set_masked_raw()
203 uint32_t mask) in gpio_mcux_lpc_port_set_bits_raw() argument
208 gpio_base->SET[config->port_no] = mask; in gpio_mcux_lpc_port_set_bits_raw()
214 uint32_t mask) in gpio_mcux_lpc_port_clear_bits_raw() argument
219 gpio_base->CLR[config->port_no] = mask; in gpio_mcux_lpc_port_clear_bits_raw()
225 uint32_t mask) in gpio_mcux_lpc_port_toggle_bits() argument
230 gpio_base->NOT[config->port_no] = mask; in gpio_mcux_lpc_port_toggle_bits()
Dgpio_rp1.c133 static int gpio_rp1_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask, in gpio_rp1_port_set_masked_raw() argument
138 sys_clear_bits(RIO_OUT_SET(data->rio_base), mask); in gpio_rp1_port_set_masked_raw()
139 sys_set_bits(RIO_OUT_CLR(data->rio_base), mask); in gpio_rp1_port_set_masked_raw()
141 sys_clear_bits(RIO_OUT_CLR(data->rio_base), (value & mask)); in gpio_rp1_port_set_masked_raw()
142 sys_set_bits(RIO_OUT_SET(data->rio_base), (value & mask)); in gpio_rp1_port_set_masked_raw()
Dgpio_brcmstb.c67 static int gpio_brcmstb_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask, in gpio_brcmstb_port_set_masked_raw() argument
72 sys_clear_bits(data->base + GIO_DATA, mask); in gpio_brcmstb_port_set_masked_raw()
73 sys_set_bits(data->base + GIO_DATA, (value & mask)); in gpio_brcmstb_port_set_masked_raw()
Dwch_gpio_ch32v00x.c71 static int gpio_ch32v00x_port_set_masked_raw(const struct device *dev, uint32_t mask, in gpio_ch32v00x_port_set_masked_raw() argument
76 config->regs->BSHR = ((~value & mask) << 16) | (value & mask); in gpio_ch32v00x_port_set_masked_raw()
Dgpio_ite_it8xxx2.c366 uint8_t mask = BIT(pin); in gpio_ite_configure() local
402 *reg_gpotr |= mask; in gpio_ite_configure()
404 *reg_gpotr &= ~mask; in gpio_ite_configure()
429 *reg_gpdr |= mask; in gpio_ite_configure()
431 *reg_gpdr &= ~mask; in gpio_ite_configure()
472 uint8_t mask = BIT(pin); in gpio_ite_get_config() local
479 if (*reg_gpotr & mask) { in gpio_ite_get_config()
504 if (*reg_gpdr & mask) { in gpio_ite_get_config()
543 gpio_port_pins_t mask, in gpio_ite_port_set_masked_raw() argument
550 *reg_gpdr = ((out & ~mask) | (value & mask)); in gpio_ite_port_set_masked_raw()
/Zephyr-latest/drivers/regulator/
Dregulator_npm1300.c182 uint8_t mask; in buck_set_voltage() local
208 mask = BIT(chan); in buck_set_voltage()
209 return mfd_npm1300_reg_update(config->mfd, BUCK_BASE, BUCK_OFFSET_SW_CTRL, mask, mask); in buck_set_voltage()
398 uint8_t mask; in regulator_npm1300_set_buck_pin_ctrl() local
404 mask = BIT(6U) | BIT_MASK(3U); in regulator_npm1300_set_buck_pin_ctrl()
409 mask = BIT(7U) | (BIT_MASK(3U) << 3U); in regulator_npm1300_set_buck_pin_ctrl()
418 mask); in regulator_npm1300_set_buck_pin_ctrl()
421 mask); in regulator_npm1300_set_buck_pin_ctrl()
424 mask); in regulator_npm1300_set_buck_pin_ctrl()
528 static int get_enabled_reg(const struct device *dev, uint8_t base, uint8_t offset, uint8_t mask, in get_enabled_reg() argument
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_xlnx_zynq.c59 LOG_DBG("0x%04x: mask 0x%08x, val 0x%08x", addr, pins[i].mask, pins[i].val); in pinctrl_configure_pins()
62 val &= ~(pins[i].mask); in pinctrl_configure_pins()
/Zephyr-latest/drivers/spi/
Dspi_litex_litespi.c124 static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t mask, in spiflash_len_mask_width_write() argument
132 tmp = mask & BIT_MASK(8); in spiflash_len_mask_width_write()
148 uint8_t mask = BIT(0); /* SPI Xfer mask*/ in spi_litex_xfer() local
150 spiflash_len_mask_width_write(len * 8, width, mask, dev_config->core_master_phyconfig_addr); in spi_litex_xfer()
164 spiflash_len_mask_width_write(len * 8, width, mask, in spi_litex_xfer()
/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl_i2c.c46 uint8_t mask, uint8_t value) in lsm6dsl_i2c_update_reg() argument
50 return i2c_reg_update_byte_dt(&cfg->bus_cfg.i2c, reg_addr, mask, value); in lsm6dsl_i2c_update_reg()
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32wb_clock.h63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
66 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
Dstm32wl_clock.h63 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
66 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
/Zephyr-latest/tests/drivers/input/kbd_matrix/
Dactual-key-mask.overlay8 actual-key-mask = <0x07 0x07 0x03>;
/Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/
Dnrf52840dk_nrf52840_sense_edge.overlay8 sense-edge-mask = <0x6>;
/Zephyr-latest/drivers/sensor/nxp/fxas21002/
Dfxas21002.h80 uint8_t mask,
144 uint8_t mask,
163 uint8_t mask,
/Zephyr-latest/drivers/sensor/st/lis2dh/
Dlis2dh_spi.c133 uint8_t mask, uint8_t value) in lis2dh_spi_update_reg() argument
138 tmp_val = (tmp_val & ~mask) | (value & mask); in lis2dh_spi_update_reg()
/Zephyr-latest/drivers/sensor/ti/opt3001/
Dopt3001.c49 uint16_t mask, uint16_t val) in opt3001_reg_update() argument
58 new_val = old_val & ~mask; in opt3001_reg_update()
59 new_val |= val & mask; in opt3001_reg_update()
/Zephyr-latest/soc/mediatek/mt8xxx/
Dsoc.c106 volatile uint32_t mask = BIT(bit & 0x1f); in set_group_bit() local
108 *p = val ? (*p | mask) : (*p & ~mask); in set_group_bit()
/Zephyr-latest/drivers/charger/
Dsbs_charger.c50 static int sbs_cmd_reg_update(const struct device *dev, uint8_t reg_addr, uint16_t mask, in sbs_cmd_reg_update() argument
61 new_val = (old_val & ~mask) | (val & mask); in sbs_cmd_reg_update()
/Zephyr-latest/drivers/serial/
Duart_sedi.c443 uint32_t mask; in uart_sedi_line_ctrl_set() local
467 uint32_t mask; in uart_sedi_line_ctrl_get() local
487 mask = 0; in uart_sedi_line_ctrl_get()
490 (uint32_t *)&mask); in uart_sedi_line_ctrl_get()
491 *val |= ((mask & SEDI_UART_RX_OE) ? UART_ERROR_OVERRUN : 0); in uart_sedi_line_ctrl_get()
492 *val |= ((mask & SEDI_UART_RX_PE) ? UART_ERROR_PARITY : 0); in uart_sedi_line_ctrl_get()
493 *val |= ((mask & SEDI_UART_RX_FE) ? UART_ERROR_FRAMING : 0); in uart_sedi_line_ctrl_get()
494 *val |= ((mask & SEDI_UART_RX_BI) ? UART_BREAK : 0); in uart_sedi_line_ctrl_get()

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