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/Zephyr-latest/drivers/bbram/
Dbbram_npcx.c25 static int get_bit_and_reset(const struct device *dev, int mask) in get_bit_and_reset() argument
27 int result = DRV_STATUS(dev) & mask; in get_bit_and_reset()
35 DRV_STATUS(dev) &= ~mask; in get_bit_and_reset()
37 DRV_STATUS(dev) = mask; in get_bit_and_reset()
/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8801.c62 uint8_t mask = BIT(pin); in gpio_it8801_configure() local
89 new_value = mask; in gpio_it8801_configure()
95 ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_sovr, mask, new_value); in gpio_it8801_configure()
141 uint8_t mask = BIT(pin); in gpio_it8801_get_config() local
170 if (value & mask) { in gpio_it8801_get_config()
210 static int gpio_it8801_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, in gpio_it8801_port_set_masked_raw() argument
216 ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_sovr, mask, value); in gpio_it8801_port_set_masked_raw()
328 uint8_t mask = BIT(pin); in gpio_it8801_pin_interrupt_configure() local
335 ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_gpier, mask, 0); in gpio_it8801_pin_interrupt_configure()
394 ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_gpisr, mask, mask); in gpio_it8801_pin_interrupt_configure()
[all …]
Dgpio_numaker.c116 static int gpio_numaker_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) in gpio_numaker_port_set_masked_raw() argument
121 gpio_base->DOUT = (gpio_base->DOUT & ~mask) | (mask & value); in gpio_numaker_port_set_masked_raw()
126 static int gpio_numaker_port_set_bits_raw(const struct device *dev, uint32_t mask) in gpio_numaker_port_set_bits_raw() argument
132 gpio_base->DOUT |= mask; in gpio_numaker_port_set_bits_raw()
137 static int gpio_numaker_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask) in gpio_numaker_port_clear_bits_raw() argument
143 gpio_base->DOUT &= ~mask; in gpio_numaker_port_clear_bits_raw()
148 static int gpio_numaker_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask) in gpio_numaker_port_toggle_bits() argument
154 gpio_base->DOUT ^= mask; in gpio_numaker_port_toggle_bits()
Dgpio_numicro.c125 uint32_t mask, in gpio_numicro_port_set_masked_raw() argument
130 cfg->regs->DATMSK = ~mask; in gpio_numicro_port_set_masked_raw()
137 uint32_t mask) in gpio_numicro_port_set_bits_raw() argument
141 cfg->regs->DATMSK = ~mask; in gpio_numicro_port_set_bits_raw()
148 uint32_t mask) in gpio_numicro_port_clear_bits_raw() argument
152 cfg->regs->DATMSK = ~mask; in gpio_numicro_port_clear_bits_raw()
158 static int gpio_numicro_port_toggle_bits(const struct device *dev, uint32_t mask) in gpio_numicro_port_toggle_bits() argument
163 cfg->regs->DOUT ^= mask; in gpio_numicro_port_toggle_bits()
Dgpio_mcux_rgpio.c164 uint32_t mask, in mcux_rgpio_port_set_masked_raw() argument
169 base->PDOR = (base->PDOR & ~mask) | (mask & value); in mcux_rgpio_port_set_masked_raw()
175 uint32_t mask) in mcux_rgpio_port_set_bits_raw() argument
179 RGPIO_PortSet(base, mask); in mcux_rgpio_port_set_bits_raw()
185 uint32_t mask) in mcux_rgpio_port_clear_bits_raw() argument
189 RGPIO_PortClear(base, mask); in mcux_rgpio_port_clear_bits_raw()
195 uint32_t mask) in mcux_rgpio_port_toggle_bits() argument
199 RGPIO_PortToggle(base, mask); in mcux_rgpio_port_toggle_bits()
Dgpio_fxl6408.c320 uint32_t mask, uint32_t value) in gpio_fxl6408_port_set_masked_raw() argument
335 reg_out = (reg_out & ~mask) | (mask & value); in gpio_fxl6408_port_set_masked_raw()
345 uint32_t mask) in gpio_fxl6408_port_set_bits_raw() argument
347 return gpio_fxl6408_port_set_masked_raw(dev, mask, mask); in gpio_fxl6408_port_set_bits_raw()
351 uint32_t mask) in gpio_fxl6408_port_clear_bits_raw() argument
353 return gpio_fxl6408_port_set_masked_raw(dev, mask, 0); in gpio_fxl6408_port_clear_bits_raw()
357 uint32_t mask) in gpio_fxl6408_port_toggle_bits() argument
372 reg_out ^= mask; in gpio_fxl6408_port_toggle_bits()
Dgpio_creg_gpio.c61 gpio_port_pins_t mask, in port_write() argument
71 *pin_val = ((*pin_val & ~mask) | (value & mask)) ^ toggle; in port_write()
83 gpio_port_pins_t mask, in port_set_masked() argument
86 return port_write(dev, mask, value, 0); in port_set_masked()
Dgpio_aw9523b.c63 const uint8_t mask = BIT(pin % 8); in gpio_aw9523b_pin_configure() local
64 const uint8_t input_en = (flags & GPIO_INPUT) ? mask : 0x00; in gpio_aw9523b_pin_configure()
65 const uint8_t out_high = (flags & GPIO_OUTPUT_INIT_HIGH) ? mask : 0x00; in gpio_aw9523b_pin_configure()
98 err = i2c_reg_update_byte_dt(&config->i2c, AW9523B_REG_CONFIG(port), mask, input_en); in gpio_aw9523b_pin_configure()
127 err = i2c_reg_update_byte_dt(&config->i2c, AW9523B_REG_OUTPUT(port), mask, out_high); in gpio_aw9523b_pin_configure()
149 static int gpio_aw9523b_port_read_write_toggle(const struct device *dev, gpio_port_pins_t mask, in gpio_aw9523b_port_read_write_toggle() argument
188 new_value = (old_value & ~mask) | (*value & mask); in gpio_aw9523b_port_read_write_toggle()
190 new_value = (old_value & ~mask) | (~old_value & mask); in gpio_aw9523b_port_read_write_toggle()
218 static int gpio_aw9523b_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, in gpio_aw9523b_port_set_masked_raw() argument
221 return gpio_aw9523b_port_read_write_toggle(dev, mask, &value, WRITE); in gpio_aw9523b_port_set_masked_raw()
[all …]
Dgpio_dw.c29 static int gpio_dw_port_set_bits_raw(const struct device *port, uint32_t mask);
31 uint32_t mask);
317 uint32_t mask, uint32_t value) in gpio_dw_port_set_masked_raw() argument
326 pins = (pins & ~mask) | (mask & value); in gpio_dw_port_set_masked_raw()
332 static int gpio_dw_port_set_bits_raw(const struct device *port, uint32_t mask) in gpio_dw_port_set_bits_raw() argument
341 pins |= mask; in gpio_dw_port_set_bits_raw()
348 uint32_t mask) in gpio_dw_port_clear_bits_raw() argument
357 pins &= ~mask; in gpio_dw_port_clear_bits_raw()
363 static int gpio_dw_port_toggle_bits(const struct device *port, uint32_t mask) in gpio_dw_port_toggle_bits() argument
372 pins ^= mask; in gpio_dw_port_toggle_bits()
Dgpio_mcux_igpio.c229 uint32_t mask, in mcux_igpio_port_set_masked_raw() argument
234 base->DR = (base->DR & ~mask) | (mask & value); in mcux_igpio_port_set_masked_raw()
240 uint32_t mask) in mcux_igpio_port_set_bits_raw() argument
244 GPIO_PortSet(base, mask); in mcux_igpio_port_set_bits_raw()
250 uint32_t mask) in mcux_igpio_port_clear_bits_raw() argument
254 GPIO_PortClear(base, mask); in mcux_igpio_port_clear_bits_raw()
260 uint32_t mask) in mcux_igpio_port_toggle_bits() argument
264 GPIO_PortToggle(base, mask); in mcux_igpio_port_toggle_bits()
Dgpio_sifive.c189 gpio_port_pins_t mask, in gpio_sifive_port_set_masked_raw() argument
194 gpio->out_val = (gpio->out_val & ~mask) | (value & mask); in gpio_sifive_port_set_masked_raw()
200 gpio_port_pins_t mask) in gpio_sifive_port_set_bits_raw() argument
204 gpio->out_val |= mask; in gpio_sifive_port_set_bits_raw()
210 gpio_port_pins_t mask) in gpio_sifive_port_clear_bits_raw() argument
214 gpio->out_val &= ~mask; in gpio_sifive_port_clear_bits_raw()
220 gpio_port_pins_t mask) in gpio_sifive_port_toggle_bits() argument
224 gpio->out_val ^= mask; in gpio_sifive_port_toggle_bits()
/Zephyr-latest/drivers/ipm/
Dipm_stm32_ipcc.c107 uint32_t mask, i; in stm32_ipcc_mailbox_rx_isr() local
109 mask = (~IPCC_ReadReg(cfg->ipcc, MR)) & IPCC_ALL_MR_RXO_CH_MASK; in stm32_ipcc_mailbox_rx_isr()
110 mask &= IPCC_ReadOtherInstReg_SR(cfg->ipcc) & IPCC_ALL_SR_CH_MASK; in stm32_ipcc_mailbox_rx_isr()
113 if (!((1 << i) & mask)) { in stm32_ipcc_mailbox_rx_isr()
134 uint32_t mask, i; in stm32_ipcc_mailbox_tx_isr() local
136 mask = (~IPCC_ReadReg(cfg->ipcc, MR)) & IPCC_ALL_MR_TXF_CH_MASK; in stm32_ipcc_mailbox_tx_isr()
137 mask = mask >> IPCC_C1MR_CH1FM_Pos; in stm32_ipcc_mailbox_tx_isr()
139 mask &= ~IPCC_ReadReg_SR(cfg->ipcc) & IPCC_ALL_SR_CH_MASK; in stm32_ipcc_mailbox_tx_isr()
142 if (!((1 << i) & mask)) { in stm32_ipcc_mailbox_tx_isr()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_b91.c129 uint8_t mask; in pinctrl_configure_pin() local
141 mask = (uint8_t) ~(BIT(offset) | BIT(offset + 1)); in pinctrl_configure_pin()
148 reg_pin_mux(pin) = (reg_pin_mux(pin) & mask) | func; in pinctrl_configure_pin()
152 analog_write_reg8(pull_up_en_addr, (analog_read_reg8(pull_up_en_addr) & mask) | pull); in pinctrl_configure_pin()
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-miwus-int-map.dtsi21 group-mask = <0x09>;
26 group-mask = <0xF0>;
37 group-mask = <0x60>;
/Zephyr-latest/drivers/display/
Ddisplay_max7219.c125 static inline uint8_t next_pixel(uint8_t *mask, uint8_t *data, const uint8_t **buf) in next_pixel() argument
127 *mask <<= 1; in next_pixel()
128 if (!*mask) { in next_pixel()
129 *mask = 0x01; in next_pixel()
132 return *data & *mask; in next_pixel()
135 static inline void skip_pixel(uint8_t *mask, uint8_t *data, const uint8_t **buf, uint16_t count) in skip_pixel() argument
138 next_pixel(mask, data, buf); in skip_pixel()
175 uint8_t mask = 0; in max7219_write() local
185 WRITE_BIT(segment, px, next_pixel(&mask, &data, &byte_buf)); in max7219_write()
188 skip_pixel(&mask, &data, &byte_buf, to_skip); in max7219_write()
/Zephyr-latest/drivers/rtc/
Drtc_rv3028.c229 static int rv3028_update_reg8(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val) in rv3028_update_reg8() argument
234 err = i2c_reg_update_byte_dt(&config->i2c, addr, mask, val); in rv3028_update_reg8()
237 mask, val, err); in rv3028_update_reg8()
350 static int rv3028_update_cfg(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val) in rv3028_update_cfg() argument
360 val_new = (val_old & ~mask) | (val & mask); in rv3028_update_cfg()
546 static int rv3028_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask) in rv3028_alarm_get_supported_fields() argument
555 *mask = RV3028_RTC_ALARM_TIME_MASK; in rv3028_alarm_get_supported_fields()
560 static int rv3028_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, in rv3028_alarm_set_time() argument
570 if (mask & ~(RV3028_RTC_ALARM_TIME_MASK)) { in rv3028_alarm_set_time()
571 LOG_ERR("unsupported alarm field mask 0x%04x", mask); in rv3028_alarm_set_time()
[all …]
/Zephyr-latest/drivers/i3c/
Di3c_mcux.c138 uint32_t mask, uint32_t match, in reg32_poll_timeout() argument
146 if (!WAIT_FOR((sys_read32((mm_reg_t)reg) & mask) == match, timeout_us, /*nop*/)) { in reg32_poll_timeout()
160 uint32_t mask, uint32_t update) in reg32_update() argument
164 val &= ~mask; in reg32_update()
165 val |= (update & mask); in reg32_update()
180 uint32_t mask, uint32_t match) in reg32_test_match() argument
184 return (val & mask) == match; in reg32_test_match()
195 static inline bool reg32_test(volatile uint32_t *reg, uint32_t mask) in reg32_test() argument
197 return reg32_test_match(reg, mask, mask); in reg32_test()
223 static void mcux_i3c_interrupt_enable(I3C_Type *base, uint32_t mask) in mcux_i3c_interrupt_enable() argument
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_agilex_ll.c21 #define mmio_setbits_32(addr, mask) sys_set_bits((addr), (mask)) argument
22 #define mmio_clrbits_32(addr, mask) sys_clear_bits((addr), (mask)) argument
/Zephyr-latest/drivers/i2c/
Di2c_litex.c44 uint32_t mask = BIT(bit); in set_bit() local
47 litex_write8(litex_read8(addr) | mask, addr); in set_bit()
49 litex_write8(litex_read8(addr) & ~mask, addr); in set_bit()
55 uint32_t mask = BIT(bit); in get_bit() local
57 return !!(litex_read8(addr) & mask); in get_bit()
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h47 #define STM32_MCO_CFGR(val, mask, shift, reg) \ argument
50 (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) | \
Dstm32l1_clock.h51 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ argument
54 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Darmv8_timer.h48 static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask) in arm_arch_timer_set_irq_mask() argument
54 if (mask) { in arm_arch_timer_set_irq_mask()
/Zephyr-latest/drivers/mfd/
Dmfd_axp192.c112 uint8_t mask; member
119 .mask = AXP192_GPIO012_FUNC_MASK,
124 .mask = AXP192_GPIO012_FUNC_MASK,
129 .mask = AXP192_GPIO012_FUNC_MASK,
134 .mask = AXP192_GPIO3_FUNC_MASK,
139 .mask = AXP192_GPIO4_FUNC_MASK,
405 gpio_reg_desc[gpio].mask, reg_cfg); in mfd_axp192_gpio_func_ctrl()
563 int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t mask) in mfd_axp192_gpio_write_port() argument
572 gpio_reg_mask = (mask & AXP192_GPIO012_OUTPUT_MASK); in mfd_axp192_gpio_write_port()
584 gpio_reg_mask = (mask >> 3U) & AXP192_GPIO34_OUTPUT_MASK; in mfd_axp192_gpio_write_port()
[all …]
/Zephyr-latest/drivers/serial/
Dleuart_gecko.c133 uint32_t mask = LEUART_IEN_TXBL | LEUART_IEN_TXC; in leuart_gecko_irq_tx_enable() local
135 LEUART_IntEnable(base, mask); in leuart_gecko_irq_tx_enable()
141 uint32_t mask = LEUART_IEN_TXBL | LEUART_IEN_TXC; in leuart_gecko_irq_tx_disable() local
143 LEUART_IntDisable(base, mask); in leuart_gecko_irq_tx_disable()
165 uint32_t mask = LEUART_IEN_RXDATAV; in leuart_gecko_irq_rx_enable() local
167 LEUART_IntEnable(base, mask); in leuart_gecko_irq_rx_enable()
173 uint32_t mask = LEUART_IEN_RXDATAV; in leuart_gecko_irq_rx_disable() local
175 LEUART_IntDisable(base, mask); in leuart_gecko_irq_rx_disable()
189 uint32_t mask = LEUART_IEN_RXDATAV; in leuart_gecko_irq_rx_ready() local
191 return (base->IEN & mask) in leuart_gecko_irq_rx_ready()
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dasm_memory_management.h50 .macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az
53 s32i \mask, \ax, 0
58 bne \ax, \mask, 1b

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