Searched refs:driven (Results 126 – 150 of 191) sorted by relevance
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| /Zephyr-latest/boards/st/stm32wb5mm_dk/doc/ |
| D | stm32wb5mm_dk.rst | 144 STM32WB5MMG System Clock could be driven by internal or external oscillator,
145 as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
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| /Zephyr-latest/boards/arduino/nano_33_iot/doc/ |
| D | index.rst | 50 driven by TCC2 instead of by GPIO.
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| /Zephyr-latest/boards/01space/esp32c3_042_oled/doc/ |
| D | index.rst | 50 It also features a 0.42 inch OLED display, driven by a SSD1306-compatible chip.
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| /Zephyr-latest/boards/seeed/lora_e5_dev_board/doc/ |
| D | lora_e5_dev_board.rst | 148 LoRa-E5 Development board System Clock could be driven by the low-power
151 By default System clock is driven by the MSI clock at 48MHz.
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| /Zephyr-latest/boards/st/b_u585i_iot02a/doc/ |
| D | index.rst | 224 B_U585I_IOT02A Discovery System Clock could be driven by an internal or external oscillator,
225 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
226 driven by 16MHz high speed internal oscillator.
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| /Zephyr-latest/boards/atmel/sam0/samc21n_xpro/doc/ |
| D | index.rst | 81 driven by TCC2 instead of by GPIO.
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| /Zephyr-latest/boards/arduino/zero/doc/ |
| D | index.rst | 52 driven by TCC2 instead of by GPIO.
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| /Zephyr-latest/doc/hardware/emulator/ |
| D | index.rst | 73 * Emulated GPIO controllers which can be driven from SW
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| /Zephyr-latest/samples/subsys/smf/smf_calculator/ |
| D | README.rst | 10 This sample creates a basic desk calculator driven by a state machine written
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| /Zephyr-latest/boards/st/stm32h7b3i_dk/doc/ |
| D | index.rst | 142 The STM32H7B3I System Clock can be driven by an internal or external oscillator,
143 as well as by the main PLL clock. By default, the System clock is driven
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| /Zephyr-latest/boards/st/nucleo_wba52cg/doc/ |
| D | nucleo_wba52cg.rst | 177 Nucleo WBA52CG System Clock could be driven by internal or external oscillator,
178 as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
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| /Zephyr-latest/boards/st/nucleo_wba55cg/doc/ |
| D | nucleo_wba55cg.rst | 186 Nucleo WBA55CG System Clock could be driven by internal or external oscillator,
187 as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
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| /Zephyr-latest/boards/st/nucleo_wl55jc/doc/ |
| D | nucleo_wl55jc.rst | 191 Nucleo WL55JC System Clock could be driven by internal or external oscillator,
192 as well as main PLL clock. By default System clock is driven by HSE clock at
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| /Zephyr-latest/boards/shields/x_nucleo_idb05a1/doc/ |
| D | index.rst | 39 This is not a problem as CS signal is software driven gpio on Arduino A1
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| /Zephyr-latest/boards/atmel/sam0/samd21_xpro/doc/ |
| D | index.rst | 80 driven by TCC0 instead of by GPIO.
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| /Zephyr-latest/boards/atmel/sam0/saml21_xpro/doc/ |
| D | index.rst | 83 driven by TCC0 instead of by GPIO.
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| /Zephyr-latest/boards/adafruit/trinket_m0/doc/ |
| D | index.rst | 52 driven by TCC0 instead of by GPIO.
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| /Zephyr-latest/boards/atmel/sam0/same54_xpro/doc/ |
| D | index.rst | 97 driven by TCC0 instead of by GPIO.
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| /Zephyr-latest/boards/ronoth/lodev/doc/ |
| D | index.rst | 80 19 PA10 USB serial Rx is driven by this pin (output) for UART1
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| /Zephyr-latest/boards/atmel/sam0/samr34_xpro/doc/ |
| D | index.rst | 84 driven by TCC0 instead of by GPIO.
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| /Zephyr-latest/boards/st/nucleo_wb55rg/doc/ |
| D | nucleo_wb55rg.rst | 191 Nucleo WB55RG System Clock could be driven by internal or external oscillator,
192 as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
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| /Zephyr-latest/boards/st/steval_stwinbx1/doc/ |
| D | index.rst | 210 STEVAL-STWINBX1 System Clock could be driven by an internal or external oscillator,
211 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 160MHz,
212 driven by 16MHz high speed external oscillator.
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| /Zephyr-latest/boards/st/sensortile_box_pro/doc/ |
| D | index.rst | 193 SensorTile.box PRO System Clock could be driven by internal or external
195 driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
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| /Zephyr-latest/boards/st/stm32wb5mmg/doc/ |
| D | stm32wb5mmg.rst | 194 STM32WB5MMG System Clock could be driven by internal or external oscillator,
195 as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
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| /Zephyr-latest/boards/renesas/rcar_salvator_x/doc/ |
| D | rcar_salvator_x.rst | 61 | I2C | i2c | interrupt driven |
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