Searched refs:define (Results 51 – 75 of 408) sorted by relevance
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22 #define RAMABLE_REGION RAM :sram0_phdr23 #define ROMABLE_REGION RAM :sram0_phdr26 #define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(XCHAL_MPU_ALIGN);27 #define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN)28 #define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(XCHAL_MPU_ALIGN)29 #define LAST_RAM_ALIGN MPU_SEGMENT_SIZE_ALIGN31 #define MPU_SEGMENT_SIZE_ALIGN . = ALIGN(4);32 #define HDR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4)33 #define HDR_4K_OR_MPU_SEGMENT_SIZE_ALIGN ALIGN(4096)36 #define PHYS_SRAM0_ADDR (DT_REG_ADDR(DT_NODELABEL(sram0)))[all …]
10 #define DT_FLASH_SIZE DT_SIZE_M(4)11 #define DT_SRAM_SIZE DT_SIZE_M(4)
8 #define SRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))9 #define SRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))10 #define DRAM_START DT_REG_ADDR(DT_NODELABEL(dram0))11 #define DRAM_SIZE DT_REG_SIZE(DT_NODELABEL(dram0))21 #define RAMABLE_REGION dram22 #define ROMABLE_REGION dram
9 #define MCO_SEL_HSE 214 #define MCO_PRE_DIV_2 4
13 #define MCO1_SEL_LSE 126 #define MCO2_SEL_HSE 2
24 #define ROMABLE_REGION FLASH26 #define ROMABLE_REGION RAM28 #define RAMABLE_REGION RAM31 #define ROM_ADDR RAM_ADDR33 #define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)37 #define ROM_END_OFFSET CONFIG_ROM_END_OFFSET39 #define ROM_END_OFFSET 043 #define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET)45 #define ROM_SIZE (CONFIG_FLASH_SIZE * 1024 - CONFIG_FLASH_LOAD_OFFSET - ROM_END_OFFSET)48 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)[all …]
11 #define DT_DRAM_SIZE DT_SIZE_K(8192)12 #define DT_DRAM_BASE 0
30 #define ROMABLE_REGION RAM31 #define RAMABLE_REGION RAM
9 #define ROMABLE_REGION RAM10 #define RAMABLE_REGION RAM12 #define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE);19 #define MMU_PAGE_ALIGN_PERM MMU_PAGE_ALIGN21 #define MMU_PAGE_ALIGN_PERM142 #define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN_PERM143 #define APP_SHARED_ALIGN MMU_PAGE_ALIGN_PERM200 #define LAST_RAM_ALIGN MMU_PAGE_ALIGN
18 use to define the Processor ID for IPCC access34 use to define the CPU ID used by HSEM
39 #define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29))40 #define SEGSTART_CACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION)41 #define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION)43 #define SEGSTART_CACHED .44 #define SEGSTART_UNCACHED .45 #define ucram RAM49 #define IDT_BASE 0xe000000050 #define IDT_SIZE 0x200056 #define NOLOAD_BASE 0x2000057 #define NOLOAD_SIZE 0x100000[all …]
12 #define DT_DRAM_BASE 015 #define DT_DRAM_SIZE DT_SIZE_K(4096)
25 #define MCO1_SEL_HSI48 430 #define MCO1_PRE_DIV_4 4
22 #define MPU_ALIGN(region_size) . = ALIGN(4)28 #define ROMABLE_REGION ROM29 #define RAMABLE_REGION RAM32 #define ROM_BASE 0x1C01010033 #define ROM_SIZE 0x5Fa0036 #define RAM_BASE 0x1C07000037 #define RAM_SIZE 0x200000
7 # define link order because that allows the build system to hook in alternative15 # Although library properties are empty per default, then we still define link
39 #define ROMABLE_REGION RAM40 #define RAMABLE_REGION RAM
22 "Otherwise, be sure to define CONFIG_64BIT appropriately.\n"31 "Otherwise, be sure to define CONFIG_64BIT appropriately.\n"
18 #define ROMABLE_REGION RAM19 #define RAMABLE_REGION RAM21 #define _VECTOR_SECTION_NAME vector22 #define _EXCEPTION_SECTION_NAME exceptions23 #define _RESET_SECTION_NAME reset
12 #define DT_FLASH_SIZE DT_SIZE_M(4)13 #define DT_SRAM_SIZE DT_SIZE_M(4)
20 #define _EXCEPTION_SECTION_NAME exceptions21 #define _RESET_SECTION_NAME reset43 #define ROM_END_OFFSET CONFIG_ROM_END_OFFSET45 #define ROM_END_OFFSET 049 #define ROMABLE_REGION FLASH51 #define ROMABLE_REGION RAM53 #define RAMABLE_REGION RAM
11 #define DT_DRAM_SIZE DT_SIZE_M(2048)
5 #define NRF_DEFAULT_IRQ_PRIORITY 5
8 /* do not define the leds on the pc7 and pb7 but pwmleds */
8 /* do not define the led on the pa5 but a pwmleds */
