Searched refs:core (Results 476 – 500 of 877) sorted by relevance
1...<<11121314151617181920>>...36
| /Zephyr-latest/subsys/net/ip/ |
| D | Kconfig.mgmt | 125 module-str = Log level for network management event core
130 bool "Stack analysis output on Net MGMT event core"
|
| /Zephyr-latest/boards/m5stack/m5stack_stamps3/doc/ |
| D | index.rst | 9 - ESP32-S3FN8 chip (240MHz dual core)
187 - `M5Stack StampS3 <https://docs.m5stack.com/en/core/StampS3>`_
|
| /Zephyr-latest/boards/nxp/frdm_mcxw72/doc/ |
| D | index.rst | 8 The MCX W72x family features a 96 MHz Arm® Cortex®-M33 core coupled with a
10 Bluetooth LE. The independent radio subsystem, with a dedicated core and
|
| /Zephyr-latest/doc/develop/tools/ |
| D | stm32cubeide.rst | 111 #. Click on :guilabel:`Select` to select your MCU. If relevant, choose also your CPU and/or core.
127 import pykwalify.core
|
| /Zephyr-latest/scripts/west_commands/runners/ |
| D | stm32flash.py | 10 from runners.core import RunnerCaps, ZephyrBinaryRunner
|
| D | trace32.py | 13 from runners.core import BuildConfiguration, RunnerCaps, RunnerConfig, ZephyrBinaryRunner
|
| D | mdb.py | 12 from runners.core import RunnerCaps, ZephyrBinaryRunner
|
| /Zephyr-latest/doc/services/debugging/ |
| D | mipi_stp_decoder.rst | 35 * When decoding nibbles, it is more efficient when core supports unaligned memory access.
|
| /Zephyr-latest/boards/renesas/rcar_h3ulcb/doc/ |
| D | rcar_h3ulcb_a57.rst | 22 * 800-MHz ARM Cortex-R7 core;
|
| /Zephyr-latest/doc/hardware/peripherals/ |
| D | sdhc.rst | 26 The core of the SDHC api is the :c:func:`sdhc_request` api. Requests contain a
|
| /Zephyr-latest/boards/weact/stm32h5_core/ |
| D | weact_stm32h5_core.dts | 14 compatible = "weact,stm32h5-core";
|
| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.dsa | 80 module-help = Enables core DSA code to output debug messages.
|
| /Zephyr-latest/boards/adafruit/feather_esp32s3/doc/ |
| D | index.rst | 15 - ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor
30 multiprocessing. Due to its dual-core architecture, each core can be enabled to
|
| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 14 SoC series (dual core ARM Cortex-A9).
|
| /Zephyr-latest/dts/riscv/openisa/ |
| D | rv32m1_zero_riscy.dtsi | 26 * these base addresses contain the Arm core vector tables if
|
| D | rv32m1_ri5cy.dtsi | 26 * these base addresses contain the Arm core vector tables if
|
| /Zephyr-latest/boards/silabs/radio_boards/xg29_rb4412a/doc/ |
| D | index.rst | 12 - CPU core: ARM Cortex®-M33 with FPU
|
| /Zephyr-latest/dts/xtensa/nxp/ |
| D | nxp_imx8m.dtsi | 25 compatible = "cdns,xtensa-core-intc";
|
| /Zephyr-latest/boards/wemos/esp32s2_lolin_mini/doc/ |
| D | index.rst | 6 ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be s…
|
| /Zephyr-latest/boards/mediatek/mt8196/ |
| D | mt8196_adsp.dts | 35 compatible = "cdns,xtensa-core-intc";
|
| /Zephyr-latest/boards/adafruit/qt_py_rp2040/doc/ |
| D | index.rst | 13 - Dual core Arm Cortex-M0+ processor running up to 133MHz
|
| /Zephyr-latest/boards/nuvoton/numaker_m2l31ki/doc/ |
| D | index.rst | 8 series MCU with ARM® -Cortex®-M23 core.
|
| /Zephyr-latest/boards/adafruit/kb2040/doc/ |
| D | index.rst | 13 - Dual core Arm Cortex-M0+ processor running up to 133MHz
|
| /Zephyr-latest/boards/renesas/ek_ra6m1/doc/ |
| D | index.rst | 7 series for applications that require a high-performance Arm® Cortex®-M4 core at
20 - 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
|
| /Zephyr-latest/boards/nxp/mcxw72_evk/doc/ |
| D | index.rst | 8 The MCX W72x family features a 96 MHz Arm® Cortex®-M33 core coupled with a
10 Bluetooth LE. The independent radio subsystem, with a dedicated core and
|
1...<<11121314151617181920>>...36
