Searched refs:core (Results 176 – 200 of 877) sorted by relevance
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1 # Microchip MEC175X MCU core series
11 This is an FPGA logic core as described by Xilinx document PG090.
16 # Disable following to assign serial ports to m4 core
6 # Place size restrictions on first image if dual core is enabled
110 /* CM4 core clock = 100MHz117 /* CM0+ core clock = 50MHz124 /* PERI core clock = 100MHz
10 - ESP32-PICO-D4 chip (240MHz dual core, Wi-Fi/BLE 5.0)89 - `M5Stack ATOM Lite docs <https://docs.m5stack.com/en/core/ATOM%20Lite>`_90 - `M5Stack ATOM Lite schematic <https://static-cdn.m5stack.com/resource/docs/products/core/atom_lit…
28 #error Cy_SysInt_Init does not support CM0p core. in Cy_SysInt_Init()
5 add_subdirectory(core)
5 # core on a special-purpose SoC which requires a complicated script to
16 - UPD301C combines a SAMD20 core and a UPD350 USB-PD controller37 is internally connected between the SAMD20 core and the UPD350.
1 # Microchip MECH172X MCU core series using MEC5 HAL and DTSI
11 * arch/arm/core/vector_table.ld when the IRQ vector table is enabled.
13 # otherwise by default they would have gone to the net core.
13 bool "HCI IPC image on network core"
