Searched refs:control (Results 251 – 275 of 757) sorted by relevance
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31 See Processor clock control register (refer 5.1 General Configuration)
162 uint32_t control; member504 current_descriptor->control = current_descriptor->status = 0; in dma_xilinx_axi_dma_clean_up_sg_descriptors()796 current_descriptor->control = (uint32_t)block_size; in dma_xilinx_axi_dma_transfer_block()799 current_descriptor->control = in dma_xilinx_axi_dma_transfer_block()800 current_descriptor->control | XILINX_AXI_DMA_SG_DESCRIPTOR_CTRL_SOF_MASK; in dma_xilinx_axi_dma_transfer_block()803 current_descriptor->control = in dma_xilinx_axi_dma_transfer_block()804 current_descriptor->control | XILINX_AXI_DMA_SG_DESCRIPTOR_CTRL_EOF_MASK; in dma_xilinx_axi_dma_transfer_block()
19 frequency-control = "host-programmable";
5 # subsystem and provides Kconfig options to control aspects of
17 :ref:`bluetooth_mesh_od_cli` to control it. The On-Demand Private Proxy Server model only accepts
21 :ref:`bluetooth_mesh_sar_cfg_cli` to control it. The SAR Configuration Server model only accepts
6 This subsystem provides control of voltage and current regulators. A common
13 functions are used to control the LEDs.
29 int "Alignment of the RTT control block"32 Specify the alignment of the RTT control block in memory. The default
52 Most of the devices in an SoC have independent power control that can111 /* turn on the domain (e.g. setup control pins to disabled) */115 /* turn off the domain (e.g. reset control pins to default state) */
59 * control the screen backlight and as touch controller interrupt.
58 /* Pin B13 is used to control VBUS Discharge for Port1 */
68 Enable control of vin-gpios and act-gpios.
45 hw-flow-control;
61 hw-flow-control;
37 .. [2] If you want to control the reset pin from the SoC, connect it to a GPIO on the SoC
51 source. The application can take over control of the
185 uint8_t control; member
48 Task watchdog channel 1 callback, thread: control
21 control the sensor.
224 hdr->control = GPTP_SYNC_CONTROL_VALUE; in gptp_prepare_sync()278 hdr->control = GPTP_FUP_CONTROL_VALUE; in gptp_prepare_follow_up()327 hdr->control = GPTP_OTHER_CONTROL_VALUE; in gptp_prepare_pdelay_req()385 hdr->control = GPTP_OTHER_CONTROL_VALUE; in gptp_prepare_pdelay_resp()444 hdr->control = GPTP_OTHER_CONTROL_VALUE; in gptp_prepare_pdelay_follow_up()518 hdr->control = GPTP_OTHER_CONTROL_VALUE; in gptp_prepare_announce()
147 if (ash->control.key_id_mode != IEEE802154_KEY_ID_MODE_IMPLICIT) { in ieee802154_validate_aux_security_hdr()152 switch (ash->control.key_id_mode) { in ieee802154_validate_aux_security_hdr()662 aux_sec->control.security_level = sec_ctx->level; in generate_aux_security_hdr()663 aux_sec->control.key_id_mode = sec_ctx->key_mode; in generate_aux_security_hdr()664 aux_sec->control.reserved = 0U; in generate_aux_security_hdr()957 if (mhr->aux_sec->control.security_level != level) { in ieee802154_decipher_data_frame()
283 config->ep_cfg_out[i].caps.control = 1; in udc_skeleton_driver_preinit()303 config->ep_cfg_in[i].caps.control = 1; in udc_skeleton_driver_preinit()
98 hw-flow-control;237 st,sdram-control = <STM32_FMC_SDRAM_NC_8
82 hw-flow-control;
