| /Zephyr-latest/drivers/pwm/ |
| D | pwm_sam.c | 34 uint32_t channel, uint64_t *cycles) in sam_pwm_get_cycles_per_sec() argument
46 static int sam_pwm_set_cycles(const struct device *dev, uint32_t channel, in sam_pwm_set_cycles() argument
55 if (channel >= PWMCHNUM_NUMBER) { in sam_pwm_set_cycles()
75 if (pwm->PWM_CH_NUM[channel].PWM_CMR != cmr) { in sam_pwm_set_cycles()
76 pwm->PWM_DIS = 1 << channel; in sam_pwm_set_cycles()
78 pwm->PWM_CH_NUM[channel].PWM_CMR = cmr; in sam_pwm_set_cycles()
79 pwm->PWM_CH_NUM[channel].PWM_CPRD = period_cycles; in sam_pwm_set_cycles()
80 pwm->PWM_CH_NUM[channel].PWM_CDTY = pulse_cycles; in sam_pwm_set_cycles()
85 pwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period_cycles; in sam_pwm_set_cycles()
86 pwm->PWM_CH_NUM[channel].PWM_CDTYUPD = pulse_cycles; in sam_pwm_set_cycles()
[all …]
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| D | pwm_shell.c | 18 uint8_t channel; member
26 .channel = 2,
38 uint32_t channel; in cmd_cycles() local
47 channel = strtoul(argv[args_indx.channel], NULL, 0); in cmd_cycles()
55 err = pwm_set_cycles(dev, channel, period, pulse, flags); in cmd_cycles()
71 uint32_t channel; in cmd_usec() local
80 channel = strtoul(argv[args_indx.channel], NULL, 0); in cmd_usec()
88 err = pwm_set(dev, channel, PWM_USEC(period), PWM_USEC(pulse), flags); in cmd_usec()
103 uint32_t channel; in cmd_nsec() local
112 channel = strtoul(argv[args_indx.channel], NULL, 0); in cmd_nsec()
[all …]
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| D | pwm_mcux_qtmr.c | 35 static int mcux_qtmr_pwm_set_cycles(const struct device *dev, uint32_t channel, in mcux_qtmr_pwm_set_cycles() argument
44 if (channel >= CHANNEL_COUNT) { in mcux_qtmr_pwm_set_cycles()
71 config->base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); in mcux_qtmr_pwm_set_cycles()
73 QTMR_StopTimer(config->base, channel); in mcux_qtmr_pwm_set_cycles()
76 config->base->CHANNEL[channel].COMP1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()
77 config->base->CHANNEL[channel].COMP2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()
80 config->base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount; in mcux_qtmr_pwm_set_cycles()
81 config->base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount; in mcux_qtmr_pwm_set_cycles()
83 reg = config->base->CHANNEL[channel].CSCTRL; in mcux_qtmr_pwm_set_cycles()
89 config->base->CHANNEL[channel].CSCTRL = reg; in mcux_qtmr_pwm_set_cycles()
[all …]
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| D | pwm_b91.c | 58 static int pwm_b91_set_cycles(const struct device *dev, uint32_t channel, in pwm_b91_set_cycles() argument
65 if (channel >= config->channels) { in pwm_b91_set_cycles()
77 pwm_invert_en(channel); in pwm_b91_set_cycles()
79 pwm_invert_dis(channel); in pwm_b91_set_cycles()
83 pwm_set_tcmp(channel, pulse_cycles); in pwm_b91_set_cycles()
84 pwm_set_tmax(channel, period_cycles); in pwm_b91_set_cycles()
87 pwm_start(channel); in pwm_b91_set_cycles()
94 uint32_t channel, uint64_t *cycles) in pwm_b91_get_cycles_per_sec() argument
99 if (channel >= config->channels) { in pwm_b91_get_cycles_per_sec()
103 if ((config->clk32k_ch_enable & BIT(channel)) != 0U) { in pwm_b91_get_cycles_per_sec()
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| D | pwm_gecko.c | 20 uint8_t channel; member
26 static int pwm_gecko_set_cycles(const struct device *dev, uint32_t channel, in pwm_gecko_set_cycles() argument
33 if (BUS_RegMaskedRead(&cfg->timer->CC[channel].CTRL, in pwm_gecko_set_cycles()
40 BUS_RegMaskedSet(&cfg->timer->ROUTE, 1 << channel); in pwm_gecko_set_cycles()
44 (channel * _TIMER_ROUTELOC0_CC1LOC_SHIFT), in pwm_gecko_set_cycles()
45 cfg->location << (channel * _TIMER_ROUTELOC0_CC1LOC_SHIFT)); in pwm_gecko_set_cycles()
46 BUS_RegMaskedSet(&cfg->timer->ROUTEPEN, 1 << channel); in pwm_gecko_set_cycles()
52 TIMER_InitCC(cfg->timer, channel, &compare_config); in pwm_gecko_set_cycles()
55 cfg->timer->CC[channel].CTRL |= (flags & PWM_POLARITY_INVERTED) ? in pwm_gecko_set_cycles()
60 TIMER_CompareBufSet(cfg->timer, channel, pulse_cycles); in pwm_gecko_set_cycles()
[all …]
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| D | pwm_max31790.c | 47 static void max31790_set_pwmfrequency(uint8_t *destination, uint8_t channel, uint8_t value) in max31790_set_pwmfrequency() argument
50 uint8_t pos = (channel / 3) * 4; in max31790_set_pwmfrequency()
56 static uint8_t max31790_get_pwmfrequency(uint8_t value, uint8_t channel) in max31790_get_pwmfrequency() argument
59 uint8_t pos = (channel / 3) * 4; in max31790_get_pwmfrequency()
163 static int max31790_set_cycles_internal(const struct device *dev, uint32_t channel, in max31790_set_cycles_internal() argument
188 max31790_set_pwmfrequency(&value_pwm_frequency, channel, pwm_frequency_channel_value); in max31790_set_cycles_internal()
219 buffer[0] = MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel); in max31790_set_cycles_internal()
226 buffer[0] = MAX31790_REGISTER_TACHTARGETCOUNTMSB(channel); in max31790_set_cycles_internal()
236 result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_FANCONFIGURATION(channel), in max31790_set_cycles_internal()
242 result = i2c_reg_write_byte_dt(&config->i2c, MAX31790_REGISTER_FANDYNAMICS(channel), in max31790_set_cycles_internal()
[all …]
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| D | pwm_gd32.c | 60 static int pwm_gd32_set_cycles(const struct device *dev, uint32_t channel, in pwm_gd32_set_cycles() argument
66 if (channel >= config->channels) { in pwm_gd32_set_cycles()
77 TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXEN(channel); in pwm_gd32_set_cycles()
83 TIMER_CHCTL2(config->reg) |= TIMER_CHCTL2_CHXP(channel); in pwm_gd32_set_cycles()
85 TIMER_CHCTL2(config->reg) &= ~TIMER_CHCTL2_CHXP(channel); in pwm_gd32_set_cycles()
89 switch (channel) { in pwm_gd32_set_cycles()
111 if ((TIMER_CHCTL2(config->reg) & TIMER_CHCTL2_CHXEN(channel)) == 0U) { in pwm_gd32_set_cycles()
115 if (channel < 2U) { in pwm_gd32_set_cycles()
121 *chctl &= ~TIMER_CHCTLX_MSK(channel); in pwm_gd32_set_cycles()
123 (8U * (channel % 2U)); in pwm_gd32_set_cycles()
[all …]
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| /Zephyr-latest/tests/drivers/build_all/dac/ |
| D | app.overlay | 37 #io-channel-cells = <1>;
43 #io-channel-cells = <1>;
54 #io-channel-cells = <1>;
61 #io-channel-cells = <1>;
67 #io-channel-cells = <1>;
84 #io-channel-cells = < 1 >;
91 #io-channel-cells = < 1 >;
98 #io-channel-cells = < 1 >;
133 #io-channel-cells = <1>;
149 #io-channel-cells = <1>;
[all …]
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| /Zephyr-latest/drivers/mipi_dsi/ |
| D | dsi_test.c | 16 static int vnd_mipi_dsi_attach(const struct device *dev, uint8_t channel, in vnd_mipi_dsi_attach() argument
20 ARG_UNUSED(channel); in vnd_mipi_dsi_attach()
26 static ssize_t vnd_mipi_dsi_transfer(const struct device *dev, uint8_t channel, in vnd_mipi_dsi_transfer() argument
30 ARG_UNUSED(channel); in vnd_mipi_dsi_transfer()
36 static int vnd_mipi_dsi_detach(const struct device *dev, uint8_t channel, in vnd_mipi_dsi_detach() argument
40 ARG_UNUSED(channel); in vnd_mipi_dsi_detach()
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| D | mipi_dsi.c | 11 ssize_t mipi_dsi_generic_read(const struct device *dev, uint8_t channel, in mipi_dsi_generic_read() argument
39 return mipi_dsi_transfer(dev, channel, &msg); in mipi_dsi_generic_read()
42 ssize_t mipi_dsi_generic_write(const struct device *dev, uint8_t channel, in mipi_dsi_generic_write() argument
68 return mipi_dsi_transfer(dev, channel, &msg); in mipi_dsi_generic_write()
71 ssize_t mipi_dsi_dcs_read(const struct device *dev, uint8_t channel, in mipi_dsi_dcs_read() argument
81 return mipi_dsi_transfer(dev, channel, &msg); in mipi_dsi_dcs_read()
84 ssize_t mipi_dsi_dcs_write(const struct device *dev, uint8_t channel, in mipi_dsi_dcs_write() argument
107 return mipi_dsi_transfer(dev, channel, &msg); in mipi_dsi_dcs_write()
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| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | mr_canhubk3.overlay | 16 group-channel = "precision";
22 channel@6 {
32 group-channel = "precision";
37 channel@2 {
49 group-channel = "precision";
54 channel@3 {
62 channel@4 {
70 channel@5 {
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| /Zephyr-latest/drivers/display/ |
| D | display_hx8394.c | 25 uint8_t channel; member
409 static ssize_t hx8394_mipi_tx(const struct device *mipi_dev, uint8_t channel, in hx8394_mipi_tx() argument
437 return mipi_dsi_transfer(mipi_dev, channel, &msg); in hx8394_mipi_tx()
511 return hx8394_mipi_tx(config->mipi_dsi, config->channel, param, 2); in hx8394_set_orientation()
561 ret = mipi_dsi_attach(config->mipi_dsi, config->channel, &mdev); in hx8394_init()
591 ret = hx8394_mipi_tx(config->mipi_dsi, config->channel, in hx8394_init()
599 ret = hx8394_mipi_tx(config->mipi_dsi, config->channel, in hx8394_init()
606 ret = hx8394_mipi_tx(config->mipi_dsi, config->channel, in hx8394_init()
613 ret = hx8394_mipi_tx(config->mipi_dsi, config->channel, in hx8394_init()
620 ret = hx8394_mipi_tx(config->mipi_dsi, config->channel, in hx8394_init()
[all …]
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | udma.c | 110 int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel) in sy1xx_udma_cancel() argument
112 uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; in sy1xx_udma_cancel()
120 int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel) in sy1xx_udma_is_ready() argument
122 uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; in sy1xx_udma_is_ready()
130 int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel) in sy1xx_udma_wait_for_finished() argument
132 uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; in sy1xx_udma_wait_for_finished()
164 int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size, in sy1xx_udma_start() argument
167 uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; in sy1xx_udma_start()
177 int32_t sy1xx_udma_get_remaining(uint32_t base, uint32_t channel) in sy1xx_udma_get_remaining() argument
179 uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; in sy1xx_udma_get_remaining()
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| /Zephyr-latest/drivers/dma/ |
| D | dma_handlers.c | 14 static inline int z_vrfy_dma_start(const struct device *dev, uint32_t channel) in z_vrfy_dma_start() argument
17 return z_impl_dma_start((const struct device *)dev, channel); in z_vrfy_dma_start()
21 static inline int z_vrfy_dma_stop(const struct device *dev, uint32_t channel) in z_vrfy_dma_stop() argument
24 return z_impl_dma_stop((const struct device *)dev, channel); in z_vrfy_dma_stop()
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| /Zephyr-latest/drivers/mbox/ |
| D | mbox_nxp_s32_mru.c | 49 static inline uintptr_t get_mbox_addr(const struct device *dev, uint32_t channel, in get_mbox_addr() argument
54 return ((uintptr_t)cfg->base + (channel + 1) * MRU_CHANNEL_OFFSET in get_mbox_addr()
58 static int nxp_s32_mru_send(const struct device *dev, uint32_t channel, in nxp_s32_mru_send() argument
66 if (channel >= MRU_MAX_CHANNELS) { in nxp_s32_mru_send()
77 tx_mbox_addr[i] = (uint32_t *)get_mbox_addr(dev, channel, i); in nxp_s32_mru_send()
83 tx_cfg.ChMBSTATAdd = (volatile uint32 *)&cfg->base->CHXCONFIG[channel].CH_MBSTAT; in nxp_s32_mru_send()
90 static int nxp_s32_mru_register_callback(const struct device *dev, uint32_t channel, in nxp_s32_mru_register_callback() argument
95 if (!is_rx_channel_valid(dev, channel)) { in nxp_s32_mru_register_callback()
99 data->cb[channel] = cb; in nxp_s32_mru_register_callback()
100 data->user_data[channel] = user_data; in nxp_s32_mru_register_callback()
[all …]
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| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | ra6-cm4-common.dtsi | 136 channel = <0>;
150 channel = <1>;
164 channel = <2>;
178 channel = <3>;
192 channel = <4>;
206 channel = <8>;
220 channel = <9>;
227 channel = <0>;
234 channel = <1>;
243 channel = <0>;
[all …]
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| /Zephyr-latest/drivers/dac/ |
| D | dac_stm32.c | 60 uint8_t channel, uint32_t value) in dac_stm32_write_value() argument
65 if (channel - STM32_FIRST_CHANNEL >= data->channel_count || in dac_stm32_write_value()
66 channel < STM32_FIRST_CHANNEL) { in dac_stm32_write_value()
67 LOG_ERR("Channel %d is not valid", channel); in dac_stm32_write_value()
78 table_channels[channel - STM32_FIRST_CHANNEL], value); in dac_stm32_write_value()
81 table_channels[channel - STM32_FIRST_CHANNEL], value); in dac_stm32_write_value()
92 uint32_t cfg_setting, channel; in dac_stm32_channel_setup() local
109 channel = table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL]; in dac_stm32_channel_setup()
117 LL_DAC_SetOutputBuffer(cfg->base, channel, cfg_setting); in dac_stm32_channel_setup()
127 LL_DAC_SetOutputConnection(cfg->base, channel, cfg_setting); in dac_stm32_channel_setup()
[all …]
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| /Zephyr-latest/samples/bluetooth/bap_broadcast_sink/boards/ |
| D | nrf52833dk_nrf52833.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| D | nrf52840dongle_nrf52840.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| D | nrf5340dk_nrf5340_cpuapp.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| /Zephyr-latest/samples/bluetooth/bap_broadcast_source/boards/ |
| D | nrf52833dk_nrf52833.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| D | nrf52840dongle_nrf52840.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| D | nrf5340dk_nrf5340_cpuapp.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| /Zephyr-latest/tests/bluetooth/shell/boards/ |
| D | nrf5340dk_nrf5340_cpuapp.overlay | 8 mic-channel-l;
9 mic-channel-r;
12 hp-channel-l;
13 hp-channel-r;
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| /Zephyr-latest/drivers/counter/ |
| D | counter_mcux_qtmr.c | 32 qtmr_channel_selection_t channel; member
58 uint32_t current = QTMR_GetCurrentTimerCount(config->base, config->channel); in mcux_qtmr_timer_handler()
60 QTMR_ClearStatusFlags(config->base, config->channel, status); in mcux_qtmr_timer_handler()
64 QTMR_DisableInterrupts(config->base, config->channel, in mcux_qtmr_timer_handler()
70 alarm_cb(dev, config->channel, current, data->alarm_user_data); in mcux_qtmr_timer_handler()
103 #define INIT_TIMER(node_id) [DT_PROP(node_id, channel)] = DEVICE_DT_GET(node_id),
128 QTMR_StartTimer(config->base, config->channel, config->mode); in DT_INST_FOREACH_STATUS_OKAY()
137 QTMR_StopTimer(config->base, config->channel); in mcux_qtmr_stop()
146 *ticks = QTMR_GetCurrentTimerCount(config->base, config->channel); in mcux_qtmr_get_value()
170 current = QTMR_GetCurrentTimerCount(config->base, config->channel); in mcux_qtmr_set_alarm()
[all …]
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