Searched refs:cache (Results 151 – 175 of 319) sorted by relevance
12345678910>>...13
475 cache = CMakeCache.from_build_dir(build_dir)476 self.cmake_cache = cache480 target = cache.get('RIMAGE_TARGET')593 cmake_default_key = cache.get('RIMAGE_SIGN_KEY', 'key placeholder from sign.py')
662 cache = CMakeCache.from_build_dir(self.build_dir)664 app_src_dir = cache.get('APPLICATION_SOURCE_DIR')665 app_bin_dir = cache.get('APPLICATION_BINARY_DIR')669 '-P', cache['ZEPHYR_BASE'] + '/cmake/pristine.cmake']
17 # This CMake modules loads the sysbuild cache variables as target properties on
303 int "The number of EID-to-RLOC cache entries"306 The number of EID-to-RLOC cache entries.309 int "The maximum number of EID-to-RLOC cache entries"312 The maximum number of EID-to-RLOC cache entries that can be used for
133 struct k_thread *cache; member
68 cache-size = <64>;
300 _kernel.ready_q.cache = thread; in update_cache()302 _kernel.ready_q.cache = _current; in update_cache()734 new_thread = _kernel.ready_q.cache; in need_swap()800 return _kernel.ready_q.cache; in z_swap_next_thread()911 z_sched_usage_switch(_kernel.ready_q.cache); in z_get_next_switch_handle()913 set_current(_kernel.ready_q.cache); in z_get_next_switch_handle()
308 _kernel.ready_q.cache != _current) { in arch_isr_direct_footer()
16 - 32KB cache for XIP and Data
19 * 32KB instruction cache20 * 32KB data cache
19 * 16 KB instruction cache.20 * 16 KB data cache.
26 use tends to incur more cache-misses as nodes are spread throughout
58 to a certain byte boundary, or dealing with cache line restrictions.
28 * mapping is set up to bypass the L1 cache, so it must be used when31 * that is managed with explicit cache flush/invalidate operations.34 * including alignment to a cache line. Be sure to also emit the446 * wants to use the cache563 * the cache remap script doesn't try to move them around needlessly.
205 ${LVGL_DIR}/src/misc/cache/lv_cache.c206 ${LVGL_DIR}/src/misc/cache/lv_cache_entry.c207 ${LVGL_DIR}/src/misc/cache/lv_cache_lru_rb.c208 ${LVGL_DIR}/src/misc/cache/lv_image_cache.c209 ${LVGL_DIR}/src/misc/cache/lv_image_header_cache.c
43 * If at least one of the cores uses data cache on shared memory, set the ``dcache-alignment`` value.45 You can skip it if none of the communication sides is using data cache on shared memory.112 This area is divided into even-sized blocks aligned to cache boundaries.114 The location of each area is calculated to fulfill cache boundary requirements and allow optimal re…122 * ``alignment`` - Memory cache alignment.126 #. Align region boundaries to cache:
116 cache-size = <4096>;120 The cache size specified in :dtcompatible:`zephyr,flash-disk` node should be
138 int "Number of entries in domain name cache"146 int "Number of entries in source name cache"
71 return &pb->ext.cache.wr_idx; in get_wr_idx_loc()81 return pb->ext.cache.data; in get_data_loc()
92 # Enable cache management features when using M7 core, since these parts
143 /* Various memory-map dependent cache attribute settings: */160 * Every 512M in 4GB space has dedicate cache attribute.162 * 2: cache bypass
20 "net arp", "Print information about IPv4 ARP cache. Only available if
