| /Zephyr-latest/share/sysbuild/cmake/modules/ |
| D | sysbuild_extensions.cmake | 11 # All CMake cache variables are stored in a custom target which is identified by
14 # IMAGE: image name identifying the cache for later sysbuild_get() lookup calls.
70 # <variable>: variable used for returning CMake cache value. Also used as lookup
72 # IMAGE: image name identifying the cache to use for variable lookup.
73 # VAR: name of the CMake cache variable name to lookup.
75 # CACHE: Flag indicating that a CMake cache variable should be fetched.
113 # This function works on the sysbuild cache for sysbuild managed applications.
116 # CREATE : Create or update existing sysbuild cache file for the application.
117 # The sysbuild cache is only updated if it contain changes.
120 # invocation if the sysbuild cache has changed. It is
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| D | sysbuild_root.cmake | 21 # Converted paths are placed in the CMake cache so that they are propagated
45 # have been added to the cache in order for the settings to propagate to images.
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| /Zephyr-latest/include/zephyr/sys/ |
| D | spsc_pbuf.h | 108 struct spsc_pbuf_ext_cache cache; member
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| /Zephyr-latest/samples/subsys/fs/littlefs/boards/ |
| D | nucleo_h743zi.overlay | 25 cache-size = <256>;
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| /Zephyr-latest/scripts/west_commands/ |
| D | run_common.py | 249 cache = load_cmake_cache(build_dir, user_args)
258 for directory in cache.get_list('SOC_DIRECTORIES'):
263 for directory in cache.get_list('BOARD_DIRECTORIES'):
341 cache = load_cmake_cache(build_dir, user_args)
355 cache)
585 def use_runner_cls(command, board, args, runners_yaml, cache): argument
599 if 'BOARD_DIR' in cache:
600 board_cmake = Path(cache['BOARD_DIR']) / 'board.cmake'
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| D | zcmake.py | 245 with open(cache_file, 'r', encoding="utf-8") as cache:
246 for line_no, line in enumerate(cache):
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| /Zephyr-latest/soc/andestech/ae350/ |
| D | Kconfig | 119 Support Andes V5 I/O Coherence Port to handle cache coherency
120 between cache and external non-caching master, such as DMA
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| /Zephyr-latest/samples/bluetooth/hci_uart_3wire/src/ |
| D | main.c | 689 struct net_buf *buf, *cache; in rx_thread() local
697 while ((cache = k_fifo_get(&h5.unack_queue, K_NO_WAIT))) { in rx_thread()
698 net_buf_unref(cache); in rx_thread()
703 while ((cache = k_fifo_get(&h5.tx_queue, K_NO_WAIT))) { in rx_thread()
704 net_buf_unref(cache); in rx_thread()
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| /Zephyr-latest/share/sysbuild/ |
| D | CMakeLists.txt | 11 # This will update the APP_DIR cache variable to PATH type and apply a comment.
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_pca95xx.c | 133 uint16_t *cache, uint16_t *buf) in read_port_regs() argument
148 *cache = value; in read_port_regs()
159 uint16_t *cache, uint16_t value) in write_port_reg() argument
178 *cache = value; in write_port_reg()
200 uint16_t *cache, uint16_t value) in write_port_regs() argument
215 *cache = value; in write_port_regs()
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| D | Kconfig.pca_series | 40 On devices w/o interrupt status, it will also cache
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| /Zephyr-latest/cmake/modules/ |
| D | FindGnuLd.cmake | 34 "GNULD_LINKER specified directly in cache, but GNULD_LINKER_IS_BFD is not "
36 "to correct value in cache to silence this warning"
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.nrfx | 57 int "TX cache buffer size"
62 For UARTE, TX cache buffer is used when provided TX buffer is not located
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| /Zephyr-latest/scripts/west_commands/completion/ |
| D | west-completion.zsh | 132 '--name-cache[name-based cache]:name cache folder:_directories'
133 '--path-cache[path-based cache]:path cache folder:_directories'
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| /Zephyr-latest/dts/x86/intel/ |
| D | atom.dtsi | 17 d-cache-line-size = <64>;
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | CMakeLists.txt | 27 zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
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| /Zephyr-latest/arch/xtensa/core/ |
| D | README_MMU.txt | 11 The Xtensa MMU operates on top of a fairly conventional TLB cache.
20 Like the L1 cache, the TLB is split into separate instruction and data
246 the L1 data cache on the CPU. If the physical memory storing page
248 page mapped within the same cache line, or to change the tables) then
249 the refill will be served from the data cache and not main memory.
252 lets the L1 data cache act as a "L2 TLB" for applications with a lot
257 But it is also important to note that the L1 data cache on Xtensa is
258 incoherent! The cache being used for refill reflects the last access
260 mapped. Page table changes in the data cache of one CPU will be
261 invisible to the data cache of another. There is no simple way of
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| /Zephyr-latest/soc/cdns/dc233c/include/ |
| D | xtensa-dc233c.ld | 89 /* Various memory-map dependent cache attribute settings:
94 * 0x3 - rwx, bypass cache
95 * 0x7 - rwx, cache write back
96 * 0xB - wrx, cache write through
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 28 * mapping is set up to bypass the L1 cache, so it must be used when
31 * that is managed with explicit cache flush/invalidate operations.
34 * including alignment to a cache line. Be sure to also emit the
375 * wants to use the cache
445 * the cache remap script doesn't try to move them around needlessly.
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| /Zephyr-latest/subsys/bluetooth/mesh/ |
| D | subnet.h | 48 uint8_t cache[8]; /* Cached last beacon auth value */ member
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| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | Kconfig | 65 bool "Code cache"
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| /Zephyr-latest/tests/boards/espressif/cache_coex/ |
| D | README.rst | 10 a common cache. It does so by allocating a big PSRAM memory chunk and repeatedly filling that region
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| /Zephyr-latest/subsys/net/lib/dns/ |
| D | Kconfig | 138 bool "DNS resolver cache"
140 This option enables the dns resolver cache. DNS queries
141 will be cached based on TTL and delivered from cache
147 int "Number of cache entries supported by the dns cache"
150 This defines how many entries the DNS cache can hold. If
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| /Zephyr-latest/doc/hardware/peripherals/ |
| D | dma.rst | 17 The DMA drivers in general do not handle cache coherency; this is left up to the developer as
19 overview of cache management in Zephyr.
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| /Zephyr-latest/subsys/net/l2/ieee802154/ |
| D | Kconfig | 89 int "IEEE 802.15.4 Reassembly cache size"
93 cache size.
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