| /Zephyr-latest/drivers/memc/ |
| D | memc_nxp_s32_qspi.c | 29 QuadSPI_Type *base; member
35 static inline uint8_t get_instance(QuadSPI_Type *base) in get_instance() argument
41 if (base_ptrs[i] == base) { in get_instance()
56 data->instance = get_instance(config->base); in memc_nxp_s32_qspi_init()
184 .base = (QuadSPI_Type *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_mcux_ctimer.c | 41 CTIMER_Type *base; member
180 status = CTIMER_SetupPwmPeriod(config->base, period_channel, pulse_channel, period_cycles, in mcux_ctimer_pwm_set_cycles()
189 CTIMER_StartTimer(config->base); in mcux_ctimer_pwm_set_cycles()
236 CTIMER_Init(config->base, &pwm_config); in mcux_ctimer_pwm_init()
266 .base = (CTIMER_Type *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/include/zephyr/arch/arc/v2/mpu/ |
| D | arc_mpu.h | 90 uint32_t base; member
99 .base = _base, \
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| /Zephyr-latest/soc/espressif/esp32c2/ |
| D | Kconfig.mac | 12 single base MAC address.
15 sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
18 …and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethern…
21 …When using the default (Espressif-assigned) base MAC address, either setting can be used. When usi…
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| /Zephyr-latest/soc/espressif/esp32c3/ |
| D | Kconfig.mac | 12 single base MAC address.
15 sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
18 …and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethern…
21 …When using the default (Espressif-assigned) base MAC address, either setting can be used. When usi…
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| /Zephyr-latest/soc/espressif/esp32c6/ |
| D | Kconfig.mac | 12 single base MAC address.
15 sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
18 …and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethern…
21 …When using the default (Espressif-assigned) base MAC address, either setting can be used. When usi…
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| /Zephyr-latest/drivers/clock_control/ |
| D | beetle_clock_control.c | 32 static inline void beetle_set_clock(volatile uint32_t *base, in beetle_set_clock() argument
41 base[0] |= (1 << bit); in beetle_set_clock()
44 base[2] |= (1 << bit); in beetle_set_clock()
47 base[4] |= (1 << bit); in beetle_set_clock()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_gecko_eusart.c | 35 EUSART_TypeDef *base; member
144 EUSART_SpiInit(gecko_config->base, &eusartInit); in spi_eusart_config()
149 gecko_config->base->CMD = (uint32_t)eusartEnable; in spi_eusart_config()
214 ret = spi_eusart_shift_frames(gecko_config->base, data); in spi_gecko_eusart_xfer()
284 if (!(gecko_config->base->STATUS & EUSART_STATUS_TXIDLE)) { in spi_gecko_eusart_release()
307 .base = (EUSART_TypeDef *)DT_INST_REG_ADDR(n), \
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| D | spi_ambiq_bleif.c | 31 uint32_t base; member
43 #define SPI_BASE (((const struct spi_ambiq_config *)(dev)->config)->base)
183 ret = am_hal_ble_initialize((cfg->base - BLEIF_BASE) / cfg->size, &data->BLEhandle); in spi_ambiq_init()
212 .base = DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/mipi_dsi/ |
| D | dsi_mcux.c | 42 MIPI_DSI_Type base; member
173 DSI_Init((MIPI_DSI_Type *)&config->base, &dsi_config); in dsi_mcux_attach()
198 mipi_dsi_dphy_bit_clk_hz = DSI_InitDphy((MIPI_DSI_Type *)&config->base, in dsi_mcux_attach()
210 DSI_SetDpiConfig((MIPI_DSI_Type *)&config->base, in dsi_mcux_attach()
286 status = DSI_TransferBlocking(&config->base, &dsi_xfer); in dsi_mcux_transfer()
344 .base = { \
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| /Zephyr-latest/drivers/video/ |
| D | video_mcux_csi.c | 22 CSI_Type *base; member
36 static void __frame_done_cb(CSI_Type *base, csi_handle_t *handle, status_t status, void *user_data) in __frame_done_cb() argument
51 status = CSI_TransferGetFullBuffer(config->base, &(data->csi_handle), &buffer_addr); in __frame_done_cb()
160 ret = CSI_Init(config->base, &data->csi_config); in video_mcux_csi_set_fmt()
165 ret = CSI_TransferCreateHandle(config->base, &data->csi_handle, __frame_done_cb, data); in video_mcux_csi_set_fmt()
203 ret = CSI_TransferStart(config->base, &data->csi_handle); in video_mcux_csi_stream_start()
225 ret = CSI_TransferStop(config->base, &data->csi_handle); in video_mcux_csi_stream_stop()
249 ret = CSI_TransferGetFullBuffer(config->base, &(data->csi_handle), in video_mcux_csi_flush()
280 ret = CSI_TransferSubmitEmptyBuffer(config->base, &data->csi_handle, in video_mcux_csi_enqueue()
494 .base = (CSI_Type *)DT_INST_REG_ADDR(0),
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| /Zephyr-latest/drivers/dma/ |
| D | dma_nxp_sdma.c | 24 SDMAARM_Type *base; member
127 SDMA_ClearChannelInterruptStatus(dev_cfg->base, 1U); in dma_nxp_sdma_isr()
130 val = SDMA_GetChannelInterruptStatus(dev_cfg->base) >> 1U; in dma_nxp_sdma_isr()
134 SDMA_ClearChannelInterruptStatus(dev_cfg->base, 1 << i); in dma_nxp_sdma_isr()
208 SDMA_StartChannelSoftware(dev_cfg->base, chan_data->index); in dma_nxp_sdma_callback()
218 SDMA_CreateHandle(&chan_data->handle, dev_cfg->base, channel, &sdma_contexts[channel]); in dma_nxp_sdma_channel_init()
337 SDMA_SetChannelPriority(dev_cfg->base, channel, DMA_NXP_SDMA_CHAN_DEFAULT_PRIO); in dma_nxp_sdma_start()
338 SDMA_StartChannelSoftware(dev_cfg->base, channel); in dma_nxp_sdma_start()
453 SDMA_Init(cfg->base, &defconfig); in dma_nxp_sdma_init()
469 .base = (SDMAARM_Type *)DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/soc/espressif/esp32s2/ |
| D | Kconfig.mac | 12 derived from a single base MAC address. If the number of universal MAC addresses is two,
16 the base MAC address. If the number of universal MAC addresses is one, only WiFi station
20 When using the default (Espressif-assigned) base MAC address, either setting can be used.
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| /Zephyr-latest/kernel/ |
| D | thread.c | 126 return thread->base.prio; in z_impl_k_thread_priority_get()
230 uint8_t thread_state = thread_id->base.thread_state; in k_thread_state_str()
337 if ((arch_current_thread()->base.thread_state & _THREAD_DUMMY) != 0) { in z_check_stack_sentinel()
526 &new_thread->base.usage, in z_setup_new_thread()
527 sizeof(new_thread->base.usage)); in z_setup_new_thread()
546 z_init_thread_base(&new_thread->base, prio, _THREAD_SLEEPING, options); in z_setup_new_thread()
611 new_thread->base.cpu_mask = 1; /* must specify only one cpu */ in z_setup_new_thread()
613 new_thread->base.cpu_mask = -1; /* allow all cpus */ in z_setup_new_thread()
631 new_thread->base.prio_deadline = 0; in z_setup_new_thread()
640 new_thread->base.usage = (struct k_cycle_stats) {}; in z_setup_new_thread()
[all …]
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| /Zephyr-latest/include/zephyr/drivers/can/ |
| D | can_mcan.h | 1345 static inline int can_mcan_sys_read_reg(mm_reg_t base, uint16_t reg, uint32_t *val) in can_mcan_sys_read_reg() argument
1347 *val = sys_read32(base + reg); in can_mcan_sys_read_reg()
1361 static inline int can_mcan_sys_write_reg(mm_reg_t base, uint16_t reg, uint32_t val) in can_mcan_sys_write_reg() argument
1363 sys_write32(val, base + reg); in can_mcan_sys_write_reg()
1381 static inline int can_mcan_sys_read_mram(mem_addr_t base, uint16_t offset, void *dst, size_t len) in can_mcan_sys_read_mram() argument
1383 volatile uint32_t *src32 = (volatile uint32_t *)(base + offset); in can_mcan_sys_read_mram()
1387 __ASSERT(base % 4U == 0U, "base must be a multiple of 4"); in can_mcan_sys_read_mram()
1395 err = sys_cache_data_invd_range((void *)(base + offset), len); in can_mcan_sys_read_mram()
1421 static inline int can_mcan_sys_write_mram(mem_addr_t base, uint16_t offset, const void *src, in can_mcan_sys_write_mram() argument
1424 volatile uint32_t *dst32 = (volatile uint32_t *)(base + offset); in can_mcan_sys_write_mram()
[all …]
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| /Zephyr-latest/soc/nxp/imx/imx6sx/ |
| D | soc_clk_freq.h | 24 uint32_t get_pwm_clock_freq(PWM_Type *base);
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| /Zephyr-latest/soc/nxp/rw/ |
| D | flexspi_clock_setup.h | 11 void set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider);
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| /Zephyr-latest/boards/shields/m5stack_core2_ext/doc/ |
| D | index.rst | 3 M5Stack-Core2 base shield
9 `M5Stack-Core2`_ comes with a base shield that is connected to the M5Stack
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_xlnx_zynq.c | 26 static mm_reg_t base = DT_INST_REG_ADDR(0); variable
51 addr = base + pins[i].offset; in pinctrl_configure_pins()
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| /Zephyr-latest/drivers/dai/intel/alh/ |
| D | alh.h | 35 #define dai_base(dai) dai->plat_data.base
98 uint32_t base; member
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/ |
| D | flash_clock_setup.h | 13 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider);
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| /Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/ |
| D | flash_clock_setup.h | 13 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider);
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| /Zephyr-latest/include/zephyr/pm/ |
| D | device.h | 165 struct pm_device_base base; member
187 struct pm_device_base base; member
195 BUILD_ASSERT(offsetof(struct pm_device, base) == 0);
196 BUILD_ASSERT(offsetof(struct pm_device_isr, base) == 0);
263 .base = Z_PM_DEVICE_BASE_INIT(obj, node_id, pm_action_cb, \
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| /Zephyr-latest/drivers/can/ |
| D | can_esp32_twai.c | 69 mm_reg_t base; member
86 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_read_reg()
95 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_write_reg()
109 mm_reg_t addr = twai_config->base + reg * sizeof(uint32_t); in can_esp32_twai_write_reg32()
279 .base = DT_INST_REG_ADDR(inst), \
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.npcx | 20 # Expose this option when the reg porperty has two register base address.
21 # i.e. One UART register bass address and one MDMA register base address.
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