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/Zephyr-latest/subsys/shell/modules/kernel_service/thread/
Dmask.c34 thread->base.cpu_mask); in cmd_kernel_thread_mask_clear()
63 thread->base.cpu_mask); in cmd_kernel_thread_mask_enable_all()
98 thread->base.cpu_mask); in cmd_kernel_thread_mask_enable()
133 thread->base.cpu_mask); in cmd_kernel_thread_mask_disable()
/Zephyr-latest/drivers/rtc/
Drtc_nxp_irtc.c15 RTC_Type *base; member
67 RTC_Type *irtc_reg = config->base; in nxp_irtc_set_time()
105 RTC_Type *irtc_reg = config->base; in nxp_irtc_get_time()
152 RTC_Type *irtc_reg = config->base; in nxp_irtc_alarm_set_time()
218 RTC_Type *irtc_reg = config->base; in nxp_irtc_alarm_get_time()
265 RTC_Type *irtc_reg = config->base; in nxp_irtc_alarm_is_pending()
327 RTC_Type *irtc_reg = config->base; in nxp_irtc_init()
344 RTC_Type *irtc_reg = config->base; in nxp_irtc_isr()
386 .base = (RTC_Type *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/soc/snps/qemu_arc/
Dlinker.ld10 * SRAM base address and size
19 * flash base address and size
/Zephyr-latest/samples/boards/nordic/clock_skew/src/
Dmain.c119 const struct timeutil_sync_instant *base = &sync_state.base; in sync_work_handler() local
134 printf(" %s", us_to_text(ref_to_us(base->ref))); in sync_work_handler()
135 ref_span_us = ref_to_us(latest->ref - base->ref); in sync_work_handler()
144 printf(" %s", us_to_text(local_to_us(base->local))); in sync_work_handler()
146 local_span_us = local_to_us(latest->local - base->local); in sync_work_handler()
/Zephyr-latest/drivers/dma/
Ddmamux_stm32.c52 uint32_t base; member
99 if (dev_config->base == DT_REG_ADDR(DT_NODELABEL(dmamux1))) { in get_dma_fops()
105 if (dev_config->base == DT_REG_ADDR(DT_NODELABEL(dmamux2))) { in get_dma_fops()
110 __ASSERT(false, "Unknown dma base address %x", dev_config->base); in get_dma_fops()
157 (DMAMUX_Channel_TypeDef *)dev_config->base; in dmamux_stm32_configure()
268 if (config->base == DT_REG_ADDR(DT_NODELABEL(dmamux1))) { in dmamux_stm32_init()
284 if (config->base == DT_REG_ADDR(DT_NODELABEL(dmamux2))) { in dmamux_stm32_init()
382 .base = DT_INST_REG_ADDR(index), \
Ddma_andes_atcdmac300.c23 #define DMA_ABORT(dev) (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x24)
25 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x30)
29 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x40 + DMA_CH_OFFSET(ch))
31 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x44 + DMA_CH_OFFSET(ch))
33 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x48 + DMA_CH_OFFSET(ch))
35 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x4C + DMA_CH_OFFSET(ch))
37 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x50 + DMA_CH_OFFSET(ch))
39 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x54 + DMA_CH_OFFSET(ch))
41 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x58 + DMA_CH_OFFSET(ch))
43 (((struct dma_atcdmac300_cfg *)dev->config)->base + 0x5C + DMA_CH_OFFSET(ch))
[all …]
/Zephyr-latest/soc/intel/intel_adsp/tools/
Dcavstool.py55 self.base = hdamem + 0x0080 + (stream_id * 0x20)
71 self.regs = Regs(self.base)
205 base = WINDOW_BASE_ACE
208 base = WINDOW_BASE
211 return (base, stride)
642 ( base, stride ) = adsp_mem_window_config()
643 return base + stride * 3
648 def win_read(base, start, length): argument
650 return b''.join(bar4_mmap[base + x].to_bytes(1, 'little')
654 log.error("IndexError in bar4_mmap[%d + %d]", base, start)
[all …]
/Zephyr-latest/subsys/jwt/
Djwt_psa.c44 builder->base, builder->buf - builder->base, in jwt_sign_impl()
/Zephyr-latest/soc/nuvoton/npcx/npcx4/
Dsoc.h32 #define THEN(base) (*(volatile uint16_t *)(base + NPCX_THEN_OFFSET)) argument
/Zephyr-latest/tests/net/lib/prometheus/formatter/src/
Dmain.c40 prometheus_collector_register_metric(&test_custom_collector, &test_counter.base); in ZTEST()
41 prometheus_collector_register_metric(&test_custom_collector, &test_counter2.base); in ZTEST()
/Zephyr-latest/soc/espressif/esp32/
DKconfig.mac12 derived from a single base MAC address. If the number of universal MAC addresses is four,
15 to the final octet of the base MAC address. If the number of universal MAC addresses is two,
17 These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address.
20 When using the default (Espressif-assigned) base MAC address, either setting can be used.
/Zephyr-latest/drivers/flash/
Dsoc_flash_xmc4xxx.c23 uint32_t base; member
63 memcpy(data, (void *)(dev_config->base + offset), len); in flash_xmc4xxx_read()
75 uint32_t flash_addr = dev_config->base; in flash_xmc4xxx_write()
135 uint32_t flash_addr = dev_config->base | 0xc000000; in flash_xmc4xxx_erase()
195 .base = DT_REG_ADDR(DT_INST(0, infineon_xmc4xxx_nv_flash)),
/Zephyr-latest/drivers/adc/
Dadc_xmc4xxx.c36 XMC_VADC_GROUP_t *base; member
49 VADC_G_TypeDef *adc_group = config->base; in adc_context_start_sampling()
72 XMC_VADC_GROUP_t *adc_group = config->base; in adc_xmc4xxx_isr()
117 XMC_VADC_GROUP_t *adc_group = config->base; in start_read()
195 VADC_G_TypeDef *adc_group = config->base; in adc_xmc4xxx_channel_setup()
250 VADC_G_TypeDef *adc_group = config->base; in adc_xmc4xxx_init()
322 .base = (VADC_G_TypeDef *)DT_INST_REG_ADDR(index), \
/Zephyr-latest/arch/arc/core/
Dthread.c52 return (thread->base.user_options & K_USER) != 0; in is_user()
254 thread->base.user_options &= ~K_FP_REGS; in arch_float_disable()
271 thread->base.user_options |= K_FP_REGS; in arch_float_enable()
312 thread->base.user_options &= ~(uint8_t)options; in arc_dsp_disable()
323 thread->base.user_options |= (uint8_t)options; in arc_dsp_enable()
339 __ASSERT(!arch_is_in_isr() && (arch_current_thread()->base.cpu_mask == BIT(id)), ""); in arc_vpx_lock()
358 __ASSERT(!arch_is_in_isr() && (arch_current_thread()->base.cpu_mask == BIT(id)), ""); in arc_vpx_unlock()
/Zephyr-latest/drivers/display/
Ddisplay_mcux_elcdif.c36 LCDIF_Type *base; member
211 ELCDIF_SetNextBufferAddr(config->base, (uint32_t)dev_data->active_fb); in mcux_elcdif_write()
218 ELCDIF_EnableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable); in mcux_elcdif_write()
274 ELCDIF_RgbModeSetPixelFormat(config->base, dev_data->rgb_mode.pixelFormat); in mcux_elcdif_set_pixel_format()
308 status = ELCDIF_GetInterruptStatus(config->base); in mcux_elcdif_isr()
309 ELCDIF_ClearInterruptStatus(config->base, status); in mcux_elcdif_isr()
310 if (config->base->CUR_BUF == ((uint32_t)dev_data->active_fb)) { in mcux_elcdif_isr()
314 ELCDIF_DisableInterrupts(config->base, kELCDIF_CurFrameDoneInterruptEnable); in mcux_elcdif_isr()
351 ELCDIF_RgbModeInit(config->base, &dev_data->rgb_mode); in mcux_elcdif_init()
352 ELCDIF_RgbModeStart(config->base); in mcux_elcdif_init()
[all …]
/Zephyr-latest/drivers/peci/
Dpeci_npcx.c27 struct peci_reg *base; member
74 struct peci_reg *const reg = config->base; in peci_npcx_configure()
120 struct peci_reg *const reg = config->base; in peci_npcx_enable()
138 struct peci_reg *const reg = config->base; in peci_npcx_transfer()
204 struct peci_reg *const reg = config->base; in peci_npcx_isr()
281 .base = (struct peci_reg *)DT_INST_REG_ADDR(0),
/Zephyr-latest/tests/ztest/base/
DCMakeLists.txt6 project(base) project
13 project(base) project
/Zephyr-latest/kernel/include/
Dtimeout_q.h49 z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks); in z_add_thread_timeout()
54 return z_abort_timeout(&thread->base.timeout); in z_abort_thread_timeout()
/Zephyr-latest/soc/espressif/esp32s3/
DKconfig.mac12 single base MAC address.
15 sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
18 …and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethern…
21 …When using the default (Espressif-assigned) base MAC address, either setting can be used. When usi…
/Zephyr-latest/drivers/pwm/
Dpwm_xlnx_axi_timer.c43 mm_reg_t base; member
53 return sys_read32(config->base + offset); in xlnx_axi_timer_read32()
62 sys_write32(value, config->base + offset); in xlnx_axi_timer_write32()
192 .base = DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/mfd/
Dmfd_nxp_lp_flexcomm.c30 LP_FLEXCOMM_Type *base; member
39 uint32_t instance = LP_FLEXCOMM_GetInstance(config->base); in nxp_lp_flexcomm_isr()
112 instance = LP_FLEXCOMM_GetInstance(config->base); in nxp_lp_flexcomm_init()
144 .base = (LP_FLEXCOMM_Type *)DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_nxp_port.c46 PORT_Type *base = ports[PORT(pins[i])]; in pinctrl_configure_pins() local
50 base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux; in pinctrl_configure_pins()
/Zephyr-latest/drivers/usb/device/
Dusb_dc_dw_stm32.h55 static inline int pwr_on_st_stm32f4_fsotg(struct usb_dwc2_reg *const base) in pwr_on_st_stm32f4_fsotg() argument
57 base->ggpio |= USB_DWC2_GGPIO_STM32_PWRDWN | USB_DWC2_GGPIO_STM32_VBDEN; in pwr_on_st_stm32f4_fsotg()
/Zephyr-latest/drivers/serial/
Duart_xlnx_uartlite.c43 mm_reg_t base; member
74 status = sys_read32(config->base + STAT_REG_OFFSET); in xlnx_uartlite_read_status()
93 return (sys_read32(config->base + RX_FIFO_OFFSET) & BIT_MASK(8)); in xlnx_uartlite_read_rx_fifo()
101 sys_write32((uint32_t)c, config->base + TX_FIFO_OFFSET); in xlnx_uartlite_write_tx_fifo()
167 sys_write32(CTRL_REG_ENABLE_INTR, config->base + CTRL_REG_OFFSET); in xlnx_uartlite_irq_enable()
177 sys_write32(0, config->base + CTRL_REG_OFFSET); in xlnx_uartlite_irq_cond_disable()
348 config->base + CTRL_REG_OFFSET); in xlnx_uartlite_init()
407 .base = DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/input/
Dinput_ite_it8xxx2_kbd.c36 struct kscan_it8xxx2_regs *base; member
63 struct kscan_it8xxx2_regs *const inst = config->base; in it8xxx2_kbd_drive_column()
99 struct kscan_it8xxx2_regs *const inst = config->base; in it8xxx2_kbd_read_row()
154 struct kscan_it8xxx2_regs *const inst = config->base; in it8xxx2_kbd_init()
244 .base = (struct kscan_it8xxx2_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0),

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