| /Zephyr-latest/drivers/serial/ |
| D | uart_altera.c | 114 mm_reg_t base; member
160 status = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_poll_in()
163 *p_char = sys_read32(config->base + ALTERA_AVALON_UART_RXDATA_REG_OFFSET); in uart_altera_poll_in()
191 status = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_poll_out()
194 sys_write32(c, config->base + ALTERA_AVALON_UART_TXDATA_REG_OFFSET); in uart_altera_poll_out()
214 sys_write32(ALTERA_AVALON_UART_CLEAR_STATUS_VAL, config->base in uart_altera_init()
229 sys_write32(data->control_val, config->base + ALTERA_AVALON_UART_CONTROL_REG_OFFSET); in uart_altera_init()
257 data->status_act = sys_read32(config->base + ALTERA_AVALON_UART_STATUS_REG_OFFSET); in uart_altera_err_check()
280 sys_write32(ALTERA_AVALON_UART_CLEAR_STATUS_VAL, config->base in uart_altera_err_check()
341 sys_write32(divisor_val, config->base + ALTERA_AVALON_UART_DIVISOR_REG_OFFSET); in uart_altera_configure()
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| D | uart_bcm2711.c | 70 static bool bcm2711_mu_lowlevel_can_getc(mem_addr_t base) in bcm2711_mu_lowlevel_can_getc() argument
72 return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_RX_READY; in bcm2711_mu_lowlevel_can_getc()
75 static bool bcm2711_mu_lowlevel_can_putc(mem_addr_t base) in bcm2711_mu_lowlevel_can_putc() argument
77 return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_TX_EMPTY; in bcm2711_mu_lowlevel_can_putc()
80 static void bcm2711_mu_lowlevel_putc(mem_addr_t base, uint8_t ch) in bcm2711_mu_lowlevel_putc() argument
83 while (!bcm2711_mu_lowlevel_can_putc(base)) { in bcm2711_mu_lowlevel_putc()
88 sys_write32(ch, base + BCM2711_MU_IO); in bcm2711_mu_lowlevel_putc()
91 static void bcm2711_mu_lowlevel_init(mem_addr_t base, bool skip_baudrate_config, in bcm2711_mu_lowlevel_init() argument
97 while (!bcm2711_mu_lowlevel_can_putc(base)) { in bcm2711_mu_lowlevel_init()
102 sys_write32(0x0, base + BCM2711_MU_CNTL); in bcm2711_mu_lowlevel_init()
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| D | uart_sy1xx.c | 16 uint32_t base; member
88 SY1XX_UDMA_WRITE_REG(config->base, SY1XX_UDMA_SETUP_REG, setup); in sy1xx_uart_configure()
128 int32_t remaining_bytes = SY1XX_UDMA_READ_REG(config->base, SY1XX_UDMA_RX_SIZE_REG); in sy1xx_uart_read()
143 SY1XX_UDMA_CANCEL_RX(config->base); in sy1xx_uart_read()
146 SY1XX_UDMA_START_RX(config->base, (int32_t)data->read, DEVICE_MAX_BUFFER_SIZE, 0); in sy1xx_uart_read()
183 if (0 == SY1XX_UDMA_IS_FINISHED_TX(config->base)) { in sy1xx_uart_write()
188 uint32_t remaining_bytes = SY1XX_UDMA_GET_REMAINING_TX(config->base); in sy1xx_uart_write()
191 SY1XX_UDMA_CANCEL_TX(config->base); in sy1xx_uart_write()
201 SY1XX_UDMA_START_TX(config->base, (uint32_t)data->write, request->data_len, 0); in sy1xx_uart_write()
291 SY1XX_UDMA_CANCEL_RX(config->base); in sy1xx_uart_init()
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| D | uart_lpc11u6x.c | 457 if (!(cfg->base->stat & LPC11U6X_UARTX_STAT_RXRDY)) { in lpc11u6x_uartx_poll_in()
460 *c = cfg->base->rx_dat; in lpc11u6x_uartx_poll_in()
468 while (!(cfg->base->stat & LPC11U6X_UARTX_STAT_TXRDY)) { in lpc11u6x_uartx_poll_out()
470 cfg->base->tx_dat = c; in lpc11u6x_uartx_poll_out()
478 if (cfg->base->stat & LPC11U6X_UARTX_STAT_OVERRUNINT) { in lpc11u6x_uartx_err_check()
481 if (cfg->base->stat & LPC11U6X_UARTX_STAT_FRAMERRINT) { in lpc11u6x_uartx_err_check()
484 if (cfg->base->stat & LPC11U6X_UARTX_STAT_PARITYERRINT) { in lpc11u6x_uartx_err_check()
505 cfg->base->brg = div & LPC11U6X_UARTX_BRG_MASK; in lpc11u6x_uartx_config_baud()
584 dev_cfg->base->cfg = 0; in lpc11u6x_uartx_configure()
590 dev_cfg->base->cfg = flags | LPC11U6X_UARTX_CFG_ENABLE; in lpc11u6x_uartx_configure()
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| /Zephyr-latest/drivers/mbox/ |
| D | mbox_nxp_imx_mu.c | 31 MU_Type *base; member
45 return MU_TriggerInterrupts(cfg->base, kMU_GenInt0InterruptTrigger >> channel); in nxp_imx_mu_send()
56 MU_SendMsg(cfg->base, channel, data32); in nxp_imx_mu_send()
101 cfg->base, kMU_GenInt0InterruptEnable | kMU_GenInt1InterruptEnable | in nxp_imx_mu_set_enabled()
107 cfg->base, kMU_GenInt0InterruptEnable | kMU_GenInt1InterruptEnable | in nxp_imx_mu_set_enabled()
129 .base = (MU_Type *)DT_INST_REG_ADDR(idx), \
135 MU_Init(nxp_imx_mu_##idx##_config.base); \
162 const uint32_t flag = MU_GetStatusFlags(config->base); in DT_INST_FOREACH_STATUS_OKAY()
166 data->received_data = MU_ReceiveMsgNonBlocking(config->base, i_channel); in DT_INST_FOREACH_STATUS_OKAY()
175 MU_ClearStatusFlags(config->base, (kMU_GenInt0Flag >> i_channel)); in DT_INST_FOREACH_STATUS_OKAY()
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| /Zephyr-latest/arch/x86/ |
| D | gen_gdt.py | 84 def chop_base_limit(base, limit): argument
86 base_lo = base & 0xFFFF
87 base_mid = (base >> 16) & 0xFF
88 base_hi = (base >> 24) & 0xFF
99 def create_code_data_entry(base, limit, dpl, flags, access): argument
102 (base, limit, dpl, flags, access))
104 base_lo, base_mid, base_hi, limit_lo, limit_hi = chop_base_limit(base,
128 def create_tss_entry(base, limit, dpl): argument
130 debug("create TSS entry: %x %x %x" % (base, limit, dpl))
133 base_lo, base_mid, base_hi, limit_lo, limit_hi, = chop_base_limit(base,
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| /Zephyr-latest/drivers/adc/ |
| D | adc_mcux_adc12.c | 25 ADC_Type *base; member
83 ADC_Type *base = config->base; in mcux_adc12_start_read() local
102 tmp32 = base->CFG1 & ~(ADC_CFG1_MODE_MASK); in mcux_adc12_start_read()
104 base->CFG1 = tmp32; in mcux_adc12_start_read()
127 ADC12_SetHardwareAverage(config->base, mode); in mcux_adc12_start_read()
178 ADC12_SetChannelConfig(config->base, channel_group, &channel_config); in mcux_adc12_start_channel()
207 ADC_Type *base = config->base; in mcux_adc12_isr() local
211 result = ADC12_GetChannelConversionValue(base, channel_group); in mcux_adc12_isr()
229 ADC_Type *base = config->base; in mcux_adc12_init() local
242 ADC12_Init(base, &adc_config); in mcux_adc12_init()
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| /Zephyr-latest/drivers/dac/ |
| D | dac_mcux_dac.c | 18 DAC_Type *base; member
53 DAC_Init(config->base, &dac_config); in mcux_dac_channel_setup()
82 DAC_EnableBuffer(config->base, false); in mcux_dac_write_value()
84 DAC_SetBufferValue(config->base, 0, value); in mcux_dac_write_value()
85 DAC_Enable(config->base, true); in mcux_dac_write_value()
102 .base = (DAC_Type *)DT_INST_REG_ADDR(n), \
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| D | dac_mcux_lpdac.c | 18 LPDAC_Type *base; member
56 DAC_Init(config->base, &dac_config); in mcux_lpdac_channel_setup()
57 DAC_Enable(config->base, false); in mcux_lpdac_channel_setup()
83 DAC_Enable(config->base, true); in mcux_lpdac_write_value()
84 DAC_SetData(config->base, value); in mcux_lpdac_write_value()
103 .base = (LPDAC_Type *)DT_INST_REG_ADDR(n), \
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| /Zephyr-latest/drivers/entropy/ |
| D | entropy_mcux_trng.c | 17 TRNG_Type *base; member
27 status = TRNG_GetRandomData(config->base, buffer, length); in entropy_mcux_trng_get_entropy()
38 .base = (TRNG_Type *)DT_INST_REG_ADDR(0)
50 status = TRNG_Init(config->base, &conf); in entropy_mcux_trng_init()
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| D | entropy_rv32m1_trng.c | 17 TRNG_Type *base; member
29 status = TRNG_GetRandomData(config->base, buffer, length); in entropy_rv32m1_trng_get_entropy()
40 .base = (TRNG_Type *)DT_INST_REG_ADDR(0)
62 status = TRNG_Init(config->base, &conf); in entropy_rv32m1_trng_init()
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_dw_common.h | 31 int dw_wdt_configure(const uint32_t base, const uint32_t config);
43 int dw_wdt_calc_period(const uint32_t base, const uint32_t clk_freq,
55 int dw_wdt_probe(const uint32_t base, const uint32_t reset_pulse_length);
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| D | wdt_xilinx_axi.c | 47 mem_addr_t base; member
82 sys_write32(CSR0_EWDT1 | CSR0_WDS, config->base + REG_TWCSR0); in wdt_xilinx_axi_setup()
83 sys_write32(CSR1_EWDT2, config->base + REG_TWCSR1); in wdt_xilinx_axi_setup()
109 sys_write32(CSR0_WDS, config->base + REG_TWCSR0); in wdt_xilinx_axi_disable()
110 sys_write32(0, config->base + REG_TWCSR1); in wdt_xilinx_axi_disable()
165 sys_write32(timer_width, config->base + REG_MWR); in wdt_xilinx_axi_install_timeout()
179 uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0); in wdt_xilinx_axi_feed()
192 sys_write32(twcsr0, config->base + REG_TWCSR0); in wdt_xilinx_axi_feed()
223 if ((sys_read32(config->base + REG_TWCSR0) & CSR0_WRS) != 0) { in z_impl_hwinfo_get_reset_cause()
242 uint32_t twcsr0 = sys_read32(config->base + REG_TWCSR0); in z_impl_hwinfo_clear_reset_cause()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_andes_atcspi200.c | 51 uint32_t base; member
66 sys_clear_bits(SPI_TIMIN(cfg->base), TIMIN_SCLK_DIV_MSK); in spi_config()
67 sys_set_bits(SPI_TIMIN(cfg->base), sclk_div); in spi_config()
70 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_SLVMODE_MSK); in spi_config()
73 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_DATA_MERGE_MSK); in spi_config()
77 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_DATA_LEN_MSK); in spi_config()
78 sys_set_bits(SPI_TFMAT(cfg->base), (data_len << TFMAT_DATA_LEN_OFFSET)); in spi_config()
82 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
84 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
88 sys_set_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
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| D | spi_mcux_dspi.c | 40 SPI_Type *base; member
91 SPI_Type *base = config->base; in spi_mcux_transfer_next_packet() local
137 DSPI_EnableDMA(base, (uint32_t)kDSPI_RxDmaEnable | in spi_mcux_transfer_next_packet()
139 DSPI_StartTransfer(base); in spi_mcux_transfer_next_packet()
145 DSPI_EnableInterrupts(base, in spi_mcux_transfer_next_packet()
197 status = DSPI_MasterTransferNonBlocking(base, &data->handle, &transfer); in spi_mcux_transfer_next_packet()
210 SPI_Type *base = config->base; in spi_mcux_isr() local
215 if (0U != (DSPI_GetStatusFlags(base) & in spi_mcux_isr()
221 DSPI_MasterTransferHandleIRQ(base, &data->handle); in spi_mcux_isr()
339 SPI_Type *base = config->base; in update_tx_dma() local
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| D | spi_cc13xx_cc26xx.c | 28 uint32_t base; member
117 SSIDisable(cfg->base); in spi_cc13xx_cc26xx_configure()
120 SSIConfigSetExpClk(cfg->base, CPU_FREQ, prot, in spi_cc13xx_cc26xx_configure()
124 sys_set_bit(cfg->base + SSI_O_CR1, 0); in spi_cc13xx_cc26xx_configure()
128 SSIEnable(cfg->base); in spi_cc13xx_cc26xx_configure()
163 SSIDataPut(cfg->base, txd); in spi_cc13xx_cc26xx_transceive()
167 SSIDataGet(cfg->base, &rxd); in spi_cc13xx_cc26xx_transceive()
195 if (SSIBusy(cfg->base)) { in spi_cc13xx_cc26xx_release()
212 if (config->base == DT_INST_REG_ADDR(0)) { in spi_cc13xx_cc26xx_pm_action()
219 SSIDisable(config->base); in spi_cc13xx_cc26xx_pm_action()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_gicv3.c | 60 mem_addr_t base; in gic_wait_rwp() local
63 base = (gic_get_rdist() + GICR_CTLR); in gic_wait_rwp()
66 base = GICD_CTLR; in gic_wait_rwp()
70 while (sys_read32(base) & rwp_mask) { in gic_wait_rwp()
140 mem_addr_t base = GET_DIST_BASE(intid); in arm_gic_irq_set_priority() local
143 sys_write32(mask, ICENABLER(base, idx)); in arm_gic_irq_set_priority()
147 sys_write8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid)); in arm_gic_irq_set_priority()
154 val = sys_read32(ICFGR(base, idx)); in arm_gic_irq_set_priority()
159 sys_write32(val, ICFGR(base, idx)); in arm_gic_irq_set_priority()
389 mem_addr_t base = gic_get_rdist() + GICR_SGI_BASE_OFF; in gicv3_cpuif_init() local
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| /Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/ |
| D | display_7seg.c | 125 int display_number(int num, unsigned int base) in display_number() argument
131 if (base > 16) { in display_number()
136 if (num <= max_negative_for_base[base] || num >= max_positive_for_base[base]) { in display_number()
148 d = num % base; in display_number()
150 num /= base; in display_number()
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| /Zephyr-latest/drivers/timer/ |
| D | sy1xx_sys_timer.c | 82 static void sy1xx_sys_timer_reload(uint32_t base, uint32_t reload_timer_ticks) in sy1xx_sys_timer_reload() argument
84 sys_write32(reload_timer_ticks, (base + SY1XX_REG_TIMER_CMP_LO_OFFS)); in sy1xx_sys_timer_reload()
87 static void sy1xx_sys_timer_cfg_auto_reload(uint32_t base) in sy1xx_sys_timer_cfg_auto_reload() argument
96 sys_write32(conf, base); in sy1xx_sys_timer_cfg_auto_reload()
109 static int32_t sy1xx_sys_timer_config(uint32_t base, struct sy1xx_timer_cfg *cfg) in sy1xx_sys_timer_config() argument
130 sy1xx_sys_timer_reload(base, timer_ticks); in sy1xx_sys_timer_config()
132 sy1xx_sys_timer_cfg_auto_reload(base); in sy1xx_sys_timer_config()
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| D | mcux_os_timer.c | 33 static OSTIMER_Type *base; variable
45 return (OSTIMER_GetCurrentTimerValue(base) + cyc_sys_compensated); in mcux_lpc_ostick_get_compensated_timer_value()
57 base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; in mcux_lpc_ostick_isr()
67 OSTIMER_SetMatchValue(base, next, NULL); in mcux_lpc_ostick_isr()
118 cyc_sys_compensated += OSTIMER_GetCurrentTimerValue(base); in mcux_lpc_ostick_set_counter_timeout()
158 OSTIMER_Init(base); in mcux_lpc_ostick_compensate_system_timer()
218 OSTIMER_SetMatchValue(base, cyc + last_count - cyc_sys_compensated, NULL); in sys_clock_set_timeout()
267 base = (OSTIMER_Type *)DT_INST_REG_ADDR(0); in sys_clock_driver_init()
274 OSTIMER_Init(base); in sys_clock_driver_init()
277 OSTIMER_SetMatchValue(base, last_count + CYC_PER_TICK, NULL); in sys_clock_driver_init()
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| /Zephyr-latest/soc/nxp/s32/s32k3/ |
| D | mpu_regions.c | 20 .base = CONFIG_SRAM_BASE_ADDRESS,
27 .base = CONFIG_FLASH_BASE_ADDRESS,
34 .base = CONFIG_SRAM_BASE_ADDRESS,
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_mcux_pwt.c | 27 PWT_Type *base; member
53 return !!(config->base->CS & PWT_CS_PWTEN_MASK); in mcux_pwt_is_active()
112 PWT_Init(config->base, &data->pwt_config); in mcux_pwt_configure_capture()
113 PWT_EnableInterrupts(config->base, in mcux_pwt_configure_capture()
143 PWT_StartTimer(config->base); in mcux_pwt_enable_capture()
157 PWT_StopTimer(config->base); in mcux_pwt_disable_capture()
225 flags = PWT_GetStatusFlags(config->base); in mcux_pwt_isr()
228 if (config->base->CR & PWT_CR_LVL_MASK) { in mcux_pwt_isr()
236 PWT_ClearStatusFlags(config->base, kPWT_CounterOverflowFlag); in mcux_pwt_isr()
240 ppw = PWT_ReadPositivePulseWidth(config->base); in mcux_pwt_isr()
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| /Zephyr-latest/arch/arm64/core/cortex_r/ |
| D | arm_mpu.c | 181 uint64_t rbar = region_conf->base & MPU_RBAR_BASE_Msk; in region_init()
195 .base = (reg).dt_addr, \
388 uint64_t base = start; in dynamic_areas_init() local
389 uint64_t limit = base + size; in dynamic_areas_init()
403 if (base >= region->base && limit <= region->limit) { in dynamic_areas_init()
433 uint64_t base, uint64_t limit, in set_region() argument
436 region->base = base; in set_region()
472 uint8_t region_num, uint64_t base, in get_underlying_region() argument
478 if (base >= region->base && limit <= region->limit) { in get_underlying_region()
497 uint64_t base, uint64_t limit, struct arm_mpu_region_attr *attr) in _insert_region() argument
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| /Zephyr-latest/drivers/pcie/endpoint/ |
| D | pcie_ep_iproc.c | 25 pcie_write32(offset, &cfg->base->paxb_config_ind_addr); in iproc_pcie_conf_read()
28 *data = pcie_read32(&cfg->base->paxb_config_ind_data); in iproc_pcie_conf_read()
39 pcie_write32(offset, &cfg->base->paxb_config_ind_addr); in iproc_pcie_conf_write()
42 pcie_write32(data, &cfg->base->paxb_config_ind_data); in iproc_pcie_conf_write()
88 &cfg->base->paxb_oarr[idx].lower); in iproc_pcie_map_addr()
89 pcie_write32(pcie_ob_base >> 32, &cfg->base->paxb_oarr[idx].upper); in iproc_pcie_map_addr()
93 &cfg->base->paxb_omap[idx].lower); in iproc_pcie_map_addr()
95 &cfg->base->paxb_omap[idx].upper); in iproc_pcie_map_addr()
278 data = pcie_read32(&cfg->base->paxb_paxb_intr_status); in iproc_pcie_flr()
282 pcie_write32(PCIE0_FLR_INTR, &cfg->base->paxb_paxb_intr_clear); in iproc_pcie_flr()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_mcux_lpi2c_rtio.c | 83 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_do_configure() local
114 LPI2C_MasterSetBaudRate(base, clock_freq, baudrate); in mcux_lpi2c_do_configure()
140 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_msg_start() local
167 status = LPI2C_MasterTransferNonBlocking(base, in mcux_lpi2c_msg_start()
174 LPI2C_MasterTransferAbort(base, &data->handle); in mcux_lpi2c_msg_start()
217 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_complete() local
226 LPI2C_MasterTransferAbort(base, &data->handle); in mcux_lpi2c_complete()
233 if (0 != (base->MSR & LPI2C_MSR_NDF_MASK)) { in mcux_lpi2c_complete()
234 LPI2C_MasterTransferAbort(base, &data->handle); in mcux_lpi2c_complete()
257 static void mcux_lpi2c_master_transfer_callback(LPI2C_Type *base, in mcux_lpi2c_master_transfer_callback() argument
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