Searched full:xtensa (Results 1 – 25 of 418) sorted by relevance
12345678910>>...17
| /Zephyr-latest/boards/qemu/xtensa/doc/ |
| D | index.rst | 6 The QEMU board configuration is used to emulate the Xtensa architecture. This board
7 configuration provides support for the Xtensa simulation environment.
27 threadA: Hello World from xtensa!
28 threadB: Hello World from xtensa!
29 threadA: Hello World from xtensa!
30 threadB: Hello World from xtensa!
31 threadA: Hello World from xtensa!
32 threadB: Hello World from xtensa!
33 threadA: Hello World from xtensa!
34 threadB: Hello World from xtensa!
[all …]
|
| /Zephyr-latest/boards/cdns/xt-sim/doc/ |
| D | index.rst | 6 The Xtensa processor architecture is a configurable, extensible, and
11 For more information, see https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable
16 The following Xtensa cores are officially supported:
23 Xtensa cores can be configured to use either internal or external timers.
31 A Linux host system is required for Xtensa development work.
35 Only Xtensa tools version ``RF-2016.4-linux`` or later are officially
60 export ARCH=xtensa
63 export XTENSA_TOOLS_PATH=/opt/xtensa/XtDevTools/install/tools/RG-2016.4-linux/XtensaTools
64 export XTENSA_BUILDS_PATH=/opt/xtensa/XtDevTools/install/builds/RG-2016.4-linux
67 elif test "${CROSS}" = zephyr-xtensa
[all …]
|
| /Zephyr-latest/arch/xtensa/ |
| D | Kconfig | 1 # XTENSA architecture configuration options
6 menu "XTENSA Options"
7 depends on XTENSA
10 default "xtensa"
31 target Xtensa core, based automatically on the details in
71 This specifies which 512M region (0-7, as defined by the Xtensa
87 Rate in HZ of the Xtensa core as measured by the value of
91 bool "Use Xtensa specific arch_spin_relax() with more NOPs"
93 Some Xtensa SoCs, especially under SMP, may need extra
103 Specify the number of NOPs in Xtensa specific
[all …]
|
| /Zephyr-latest/tests/subsys/llext/ |
| D | testcase.yaml | 35 arch_allow: # Xtensa needs writable storage
45 arch_allow: arm # Xtensa needs writable storage, currently not supported on RISC-V
64 - xtensa
68 - qemu_xtensa/dc233c # Xtensa ISA
76 - xtensa
85 - qemu_xtensa/dc233c # Xtensa ISA
93 # storage to cover both ARM and Xtensa architectures on the same test.
97 - xtensa
101 - qemu_xtensa/dc233c # Xtensa ISA
110 - xtensa
[all …]
|
| /Zephyr-latest/doc/develop/toolchains/ |
| D | cadence_xcc.rst | 3 Cadence Tensilica Xtensa C/C++ Compiler (XCC)
9 * The Xtensa Xplorer which contains the necessary executables and
12 * A SoC-specific add-on to be installed on top of Xtensa Xplorer.
16 #. Install Xtensa Xplorer and then the SoC add-on.
42 * Set :envvar:`TOOLCHAIN_VER` to the Xtensa SDK version.
49 to the Xtensa SDK version.
51 #. For example, assuming the SDK is installed in ``/opt/xtensa``, and
61 export XTENSA_TOOLCHAIN_PATH=/opt/xtensa/XtDevTools/install/tools/
71 export XTENSA_TOOLCHAIN_PATH=/opt/xtensa/XtDevTools/install/tools/
86 clang-3.9: error: Xtensa-as command failed with exit code 1
|
| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.xtensa | 7 bool "Xtensa timer support"
8 depends on XTENSA
12 Enables a system timer driver for Xtensa based on the CCOUNT
21 used for the system timer. Xtensa CPUs have hard-configured
|
| /Zephyr-latest/include/zephyr/arch/xtensa/ |
| D | exception.h | 9 * @brief Xtensa public exception handling
11 * Xtensa-specific kernel exception handling interface. Included by
12 * arch/xtensa/arch.h.
24 /* Xtensa uses a variable length stack frame depending on how many
|
| D | arch.h | 8 * @brief Xtensa specific kernel interface header
9 * This header contains the Xtensa specific kernel interface. It is included
26 #include <zephyr/arch/xtensa/syscall.h>
27 #include <zephyr/arch/xtensa/thread.h>
28 #include <zephyr/arch/xtensa/irq.h>
29 #include <xtensa/config/core.h>
31 #include <zephyr/arch/xtensa/gdbstub.h>
33 #include <zephyr/arch/xtensa/thread_stack.h>
39 #include <zephyr/arch/xtensa/xtensa_mmu.h>
43 #include <zephyr/arch/xtensa/mpu.h>
[all …]
|
| /Zephyr-latest/dts/xtensa/amd/ |
| D | acp_6_0.dtsi | 7 #include <xtensa/xtensa.dtsi>
17 compatible = "cdns,tensilica-xtensa-lx7";
|
| /Zephyr-latest/cmake/toolchain/xtools/ |
| D | target.cmake | 8 set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf)
16 if("${ARCH}" STREQUAL "xtensa")
17 set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SOC_NAME}/${SYSROOT_TARGET})
18 …set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SOC_NAME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE…
|
| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.esp32 | 1 # Espressif's Interrupt Allocator driver for Xtensa SoCs
7 bool "Interrupt allocator for Xtensa-based Espressif SoCs"
12 Enable custom interrupt allocator for Espressif SoCs based on Xtensa
|
| /Zephyr-latest/arch/xtensa/core/ |
| D | debug_helpers_asm.S | 7 #include <xtensa/coreasm.h>
8 #include <xtensa/corebits.h>
9 #include <xtensa/config/system.h>
10 #include <xtensa/hal.h>
|
| /Zephyr-latest/dts/bindings/cpu/ |
| D | espressif,xtensa-lx6.yaml | 4 description: Espressif Xtensa CPU
6 compatible: "espressif,xtensa-lx6"
8 include: cdns,tensilica-xtensa-lx6.yaml
|
| D | espressif,xtensa-lx7.yaml | 4 description: Espressif Xtensa CPU
6 compatible: "espressif,xtensa-lx7"
8 include: cdns,tensilica-xtensa-lx7.yaml
|
| D | cdns,tensilica-xtensa-lx3.yaml | 4 description: Cadence Tensilica Xtensa LX3 CPU
6 compatible: "cdns,tensilica-xtensa-lx3"
|
| D | cdns,tensilica-xtensa-lx4.yaml | 4 description: Cadence Tensilica Xtensa LX4 CPU
6 compatible: "cdns,tensilica-xtensa-lx4"
|
| D | cdns,tensilica-xtensa-lx6.yaml | 4 description: Cadence Tensilica Xtensa LX6 CPU
6 compatible: "cdns,tensilica-xtensa-lx6"
|
| /Zephyr-latest/cmake/toolchain/espressif/ |
| D | target.cmake | 10 set(CROSS_COMPILE_TARGET_xtensa_esp32 xtensa-esp32-elf)
11 set(CROSS_COMPILE_TARGET_xtensa_esp32s2 xtensa-esp32s2-elf)
12 set(CROSS_COMPILE_TARGET_xtensa_esp32s3 xtensa-esp32s3-elf)
|
| /Zephyr-latest/boards/qemu/xtensa/ |
| D | qemu_xtensa_sample_controller32_mpu.yaml | 2 name: QEMU Emulation for Xtensa with MPU
6 arch: xtensa
|
| D | qemu_xtensa_dc233c.yaml | 2 name: QEMU Emulation for Xtensa
6 arch: xtensa
|
| D | qemu_xtensa_dc233c_mmu.yaml | 2 name: QEMU Emulation for Xtensa with MMU
6 arch: xtensa
|
| /Zephyr-latest/modules/ |
| D | Kconfig.xtensa | 7 Build the Xtensa HAL module during build process.
8 This is selected by the Xtensa ARCH kconfig automatically.
|
| /Zephyr-latest/scripts/west_commands/runners/ |
| D | xtensa.py | 17 return 'xtensa'
26 help='path to XTensa tools')
30 # Override any GDB with the one provided by the XTensa tools.
|
| /Zephyr-latest/boards/amd/acp_6_0_adsp/doc/ |
| D | index.rst | 6 ACP 6.0 is Audio co-processor in AMD SoC based on HiFi5 DSP Xtensa Architecture,
11 Xtensa OS (XTOS) and run on a ACP 6.0 AMD platforms.
47 Xtensa Toolchain (optional)
52 building with the proprietary Xtensa toolchain from Cadence
57 instructions from Xtensa documentation.
59 If you choose to build with the Xtensa toolchain instead of the Zephyr SDK, set
61 Xtensa toolchain environment variable listed below.
|
| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | cdns,xtensa-core-intc.yaml | 1 description: Xtensa Core interrupt controller
3 compatible: "cdns,xtensa-core-intc"
|
12345678910>>...17
