| /Zephyr-latest/drivers/serial/ |
| D | uart_renesas_ra.c | 54 #define SCR 0x02 /*!< Serial Control Register */ macro
89 * SCR (Serial Control Register)
236 if ((uart_ra_read_8(dev, SCR) & REG_MASK(SCR_RIE))) { in uart_ra_poll_in()
265 reg_val = uart_ra_read_8(dev, SCR); in uart_ra_poll_out()
266 uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE)); in uart_ra_poll_out()
274 uart_ra_write_8(dev, SCR, reg_val); in uart_ra_poll_out()
324 reg_val = uart_ra_read_8(dev, SCR); in uart_ra_configure()
326 uart_ra_write_8(dev, SCR, reg_val); in uart_ra_configure()
339 reg_val = uart_ra_read_8(dev, SCR); in uart_ra_configure()
341 uart_ra_write_8(dev, SCR, reg_val); in uart_ra_configure()
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| D | uart_renesas_ra_sci.c | 364 cfg->regs->SCR |= (R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); in uart_ra_sci_irq_tx_enable()
371 cfg->regs->SCR &= ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); in uart_ra_sci_irq_tx_disable()
459 uint8_t scr; in uart_ra_sci_irq_is_pending() local
465 scr = cfg->regs->SCR; in uart_ra_sci_irq_is_pending()
467 ret = ((scr & R_SCI0_SCR_TIE_Msk) && in uart_ra_sci_irq_is_pending()
469 ((scr & R_SCI0_SCR_RIE_Msk) && in uart_ra_sci_irq_is_pending()
476 scr = cfg->regs->SCR; in uart_ra_sci_irq_is_pending()
478 ret = ((scr & R_SCI0_SCR_TIE_Msk) && in uart_ra_sci_irq_is_pending()
480 ((scr & R_SCI0_SCR_RIE_Msk) && in uart_ra_sci_irq_is_pending()
670 cfg->regs->SCR &= (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); in disable_tx()
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| D | uart_lpc11u6x.h | 114 volatile uint32_t scr; /* Scratch pad */ member
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| /Zephyr-latest/dts/bindings/dma/ |
| D | brcm,iproc-pax-dma-v1.yaml | 21 scr-addr-loc:
25 scr-size-loc:
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| D | brcm,iproc-pax-dma-v2.yaml | 21 scr-addr-loc:
25 scr-size-loc:
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| /Zephyr-latest/subsys/sd/ |
| D | sdmmc.c | 21 static inline void sdmmc_decode_scr(struct sd_scr *scr, uint32_t *raw_scr, uint8_t *version) in sdmmc_decode_scr() argument
25 scr->flags = 0U; in sdmmc_decode_scr()
26 scr->scr_structure = (uint8_t)((raw_scr[0U] & 0xF0000000U) >> 28U); in sdmmc_decode_scr()
27 scr->sd_spec = (uint8_t)((raw_scr[0U] & 0xF000000U) >> 24U); in sdmmc_decode_scr()
29 scr->flags |= SD_SCR_DATA_STATUS_AFTER_ERASE; in sdmmc_decode_scr()
31 scr->sd_sec = (uint8_t)((raw_scr[0U] & 0x700000U) >> 20U); in sdmmc_decode_scr()
32 scr->sd_width = (uint8_t)((raw_scr[0U] & 0xF0000U) >> 16U); in sdmmc_decode_scr()
34 scr->flags |= SD_SCR_SPEC3; in sdmmc_decode_scr()
36 scr->sd_ext_sec = (uint8_t)((raw_scr[0U] & 0x7800U) >> 10U); in sdmmc_decode_scr()
37 scr->cmd_support = (uint8_t)(raw_scr[0U] & 0x3U); in sdmmc_decode_scr()
[all …]
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| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | power.c | 37 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pm_state_set()
60 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); in pm_state_exit_post_ops()
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| /Zephyr-latest/soc/nxp/kinetis/ke1xz/ |
| D | power.c | 35 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pm_state_set()
57 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); in pm_state_exit_post_ops()
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| /Zephyr-latest/dts/common/broadcom/ |
| D | viper-common.dtsi | 67 scr-addr-loc = <0x200061f0>;
68 scr-size-loc = <0x200061f8>;
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_poweroff.c | 17 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in soc_core_sleepdeep_enable()
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| D | soc_sam4l_poweroff.c | 17 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in soc_core_sleepdeep_enable()
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| /Zephyr-latest/soc/microchip/mec/mec172x/ |
| D | power.c | 72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
89 SCB->SCR &= ~BIT(2); in z_power_soc_deep_sleep()
129 SCB->SCR &= ~BIT(2); in z_power_soc_sleep()
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | device_power.c | 41 SCB->SCR &= ~(1ul << 2); in soc_lite_sleep_enable()
52 SCB->SCR = (1ul << 2); /* Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_enable()
65 SCB->SCR &= ~(1ul << 2); /* disable Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_disable()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_pw.c | 307 uint32_t ctrlr0, scr; in spi_pw_config_clk() local
309 /* Update scr control bits */ in spi_pw_config_clk()
311 scr = PW_SPI_BR_2MHZ; in spi_pw_config_clk()
313 scr = (info->clock_freq / PW_SPI_BR_MAX_FRQ) - 1; in spi_pw_config_clk()
315 scr = (info->clock_freq / config->frequency) - 1; in spi_pw_config_clk()
320 ctrlr0 |= (scr << PW_SPI_SCR_SHIFT); in spi_pw_config_clk()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | power.c | 106 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in lpm_enter_sleep_mode()
109 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in lpm_enter_sleep_mode()
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | cpu_idle.c | 27 SCB->SCR = SCB_SCR_SEVONPEND_Msk; in z_arm_cpu_idle_init()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | power.c | 240 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in system_enter_sleep()
243 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in system_enter_sleep()
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp.c | 416 * \brief Finds valid M/(N * SCR) values for given frequencies.
419 * \param[out] out_scr_div SCR divisor.
431 /* check if just SCR is enough */ in dai_ssp_find_mn()
445 /* odd SCR gives lower duty cycle */ in dai_ssp_find_mn()
450 /* clamp to valid SCR range */ in dai_ssp_find_mn()
479 * Clock that can use just SCR is preferred.
482 * \param[out] scr_div SCR divisor.
567 * \param[out] scr_div SCR divisor.
628 * \brief Finds valid M/(N * SCR) values for source clock that is already locked
631 * \param[out] scr_div SCR divisor.
[all …]
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_sam4l_twim.c | 298 twim->SCR = ~0UL; /* Clear the status flags */ in i2c_start_xfer()
496 twim->SCR = ~0UL; in i2c_sam_twim_isr()
573 twim->SCR = ~0UL; in i2c_sam_twim_initialize()
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| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_uart.h | 173 volatile uint8_t SCR; member
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| /Zephyr-latest/boards/lowrisc/opentitan_earlgrey/doc/ |
| D | index.rst | 76 …8-fastbuild-ST-2cc462681f62/bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.39.scr.vmem \
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| /Zephyr-latest/drivers/timer/ |
| D | riscv_machine_timer.c | 65 /* scr,machine-timer*/
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_cdns.c | 124 * default max speed is 25MHZ, as per SCR register in sdhc_cdns_get_host_props()
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| /Zephyr-latest/scripts/build/ |
| D | gen_kobject_list.py | 148 scr = os.path.basename(sys.argv[0]) variable
153 sys.stdout.write(scr + ": " + text + "\n")
156 sys.exit("%s ERROR: %s" % (scr, text))
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_mchp_xec.c | 209 SCB->SCR &= ~BIT(2); in pcr_slp_init()
1004 SCB->SCR |= BIT(2); in mchp_xec_clk_ctrl_sys_sleep_enable()
1012 SCB->SCR &= ~BIT(2); in mchp_xec_clk_ctrl_sys_sleep_disable()
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