| /hal_rpi_pico-latest/src/rp2_common/pico_aon_timer/include/pico/ |
| D | aon_timer.h | 18 * \brief High Level "Always on Timer" Abstraction
21 * This library uses the RTC on RP2040.
24 * This library uses the Powman Timer on RP2350.
32 …* On RP2040 the non 'calendar date/time' methods must convert the linear time value to a calendar …
42 …ilable, otherwise you might consider the method variants ending in `_calendar()` instead on RP2040.
47 …* On RP2350 the 'calendar date/time' methods must convert the calendar date/time to a linear time…
56 …le, otherwise you might consider the method variants not ending in `_calendar()` instead on RP2350.
86 * See \ref rp2040_caveats "caveats" for using this method on RP2040
98 * See \ref rp2040_caveats "caveats" for using this method on RP2040
102 * \return true on success, false if internal time format conversion failed
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| /hal_rpi_pico-latest/src/rp2_common/hardware_irq/include/hardware/ |
| D | irq.h | 43 …* On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied t…
51 …* \note You should not enable the same (shared) IRQ number on both cores, as this will lead to rac…
52 …* or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one c…
53 * on the other core.
56 …) at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Ea…
57 …et_exclusive_handler() at runtime to install a single handler for the interrupt on the current core
58 …. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and
69 * On RP2040 the interrupt numbers are as follows:
102 * On RP2350 the interrupt numbers are as follows:
213 * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
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| /hal_rpi_pico-latest/src/rp2_common/hardware_timer/include/hardware/ |
| D | timer.h | 26 * The timer peripheral on RP-series microcontrollers supports the following features:
30 * - Four alarms: match on the lower 32 bits of counter, IRQ on match.
33 …* On RP2040, by default the timer uses a one microsecond reference that is generated in the Watchd…
38 …* On RP2350, by default the timer uses a one microsecond reference that is generated by the tick b…
41 …* The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on …
101 …* \brief Returns the \ref irq_num_t for the alarm interrupt from the given alarm on the given time…
157 * On RP2040 this must be 0 as there is only one timer instance
160 * On RP2040 this may be set to 0 or 1
171 …* \brief Returns the default timer instance on the platform based on the setting of PICO_DEFAULT_T…
178 #error Setting PICO_DEFAULT_TIMER to non zero is meaningless as there is only one TIMER instance on…
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| /hal_rpi_pico-latest/src/host/hardware_irq/include/hardware/ |
| D | irq.h | 38 …* On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied t…
46 …* \note You should not enable the same (shared) IRQ number on both cores, as this will lead to rac…
47 …* or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one c…
48 * on the other core.
51 …) at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Ea…
52 …et_exclusive_handler() at runtime to install a single handler for the interrupt on the current core
53 …. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and
141 * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
153 * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
163 /*! \brief Enable or disable a specific interrupt on the executing core
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| /hal_rpi_pico-latest/src/rp2_common/pico_double/ |
| D | double_fma_dcp.S | 148 // todo optimize this based on final decision on saving_func_entry
160 // todo optimize this based on final decision on saving_func_entry
171 // todo optimize this based on final decision on saving_func_entry
189 // todo optimize this based on final decision on saving_func_entry
203 // todo optimize this based on final decision on saving_func_entry
218 // todo optimize this based on final decision on saving_func_entry
259 // todo optimize this based on final decision on saving_func_entry
271 // todo optimize this based on final decision on saving_func_entry
282 // todo optimize this based on final decision on saving_func_entry
290 // todo optimize this based on final decision on saving_func_entry
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| /hal_rpi_pico-latest/src/rp2_common/pico_multicore/include/pico/ |
| D | multicore.h | 25 * \brief Adds support for running code on, and interacting with the second processor core (core 1).
45 * \brief Returns the \ref irq_num_t for the FIFO IRQ on the given core.
48 * On RP2040 each core has a different IRQ number: `SIO_IRQ_PROC0` and `SIO_IRQ_PROC1`.
51 * On RP2350 both cores share the same irq number (`SIO_IRQ_PROC`) just with a different SIO
52 * interrupt output routed to that IRQ input on each core.
75 /*! \brief Run code on core 1
78 …* Wake up (a previously reset) core 1 and enter the given function on core 1 using the default cor…
89 /*! \brief Launch code on core 1 with stack
92 …* Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stac…
105 /*! \brief Launch code on core 1 with no stack protection
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| /hal_rpi_pico-latest/src/rp2_common/hardware_adc/include/hardware/ |
| D | adc.h | 26 * - 4 inputs that are available on package pins shared with GPIO[29:26]
33 * - 4 inputs available on QFN-60 package pins shared with GPIO[29:26]
34 * - 8 inputs available on QFN-80 package pins shared with GPIO[47:40]
44 …* RP2040, RP2350 QFN-60: User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on inp…
45 * RP2350 QFN-80 : User ADC inputs are on 0-7 (GPIO 40-47), the temperature sensor is on input 8.
67 * The ADC channel number of the on-board temperature sensor
93 …r to use. Allowable GPIO numbers are 26 to 29 inclusive on RP2040 or RP2350A, 40-48 inclusive on R…
109 * On RP02040 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
112 * On RP2350A 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
113 * On RP2350B 0...7 are GPIOs 40...47 respectively. Input 8 is the onboard temperature sensor.
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| /hal_rpi_pico-latest/src/rp2_common/hardware_pio/include/hardware/ |
| D | pio.h | 26 // PICO_CONFIG: PICO_PIO_VERSION, PIO hardware version, type=int, default=0 on RP2040 and 1 on RP23…
58 * purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism,
71 * code that needs to run on both the RP2040 and the RP2350.
75 * On RP2040, pin numbers may always be specified from 0-31
79 * On RP2350A, pin numbers may always be specified from 0-31.
81 * On RP2350B, there are 48 pins but each PIO instance can only address 32 pins (the PIO
82 * instance either addresses pins 0-31 or 16-47 based on \ref pio_set_gpio_base). The
195 …\ref gpio_function_t needed to select the PIO function for the given PIO instance on the given GPIO
207 …_num_t used for pacing DMA transfers to or from a given state machine's FIFOs on this PIO instance.
242 * On RP2040, pin numbers may always be specified from 0-31
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| /hal_rpi_pico-latest/src/rp2_common/hardware_exception/include/hardware/ |
| D | exception.h | 40 * On Arm these are vector table indices:
57 * On RISC-V these are exception cause numbers:
123 /*! \brief Set the exception handler for an exception on the executing core.
126 …* This method will assert if an exception handler has been set for this exception number on this c…
138 /*! \brief Restore the original exception handler for an exception on this core
141 …* This method may be used to restore the exception handler for an exception on this core to the st…
171 * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
175 * Only the top 4 bits are significant on ARM Cortex-M33 on RP2350, and exception priorities
176 * are not supported on RISC-V
188 * Only the top 2 bits are significant on ARM Cortex-M0+ on RP2040.
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| /hal_rpi_pico-latest/src/rp2_common/pico_flash/include/pico/ |
| D | flash.h | 22 … is being used, then the problem is simple - just disable interrupts; however if code is running on
24 * complete control of the code running on that core at all times.
29 …* How it does this is dependent on the supported environment (Free RTOS SMP or pico_multicore). Ad…
33 * otherwise returning an error (or an assert depending on \ref PICO_FLASH_ASSERT_ON_UNSAFE).
42 …* 3. pico_multicore without \ref flash_safe_execute_core_init() having been called on the other co…
43 …* \ref flash_safe_execute method does not know if code is executing on the other core, so it has t…
44 …* way, it is not able to intervene if \ref flash_safe_execute_core_init() has not been called on t…
61 …* \return true on success; there is no need to call \ref flash_safe_execute_core_deinit() on failu…
68 * \return true on success
80 * \return PICO_OK on success (the function will have been called).
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| /hal_rpi_pico-latest/src/rp2350/hardware_regs/include/hardware/regs/ |
| D | bootram.h | 51 // on successful claim is 1 << n, and on failed claim is zero.
61 // on successful claim is 1 << n, and on failed claim is zero.
71 // on successful claim is 1 << n, and on failed claim is zero.
81 // on successful claim is 1 << n, and on failed claim is zero.
91 // on successful claim is 1 << n, and on failed claim is zero.
101 // on successful claim is 1 << n, and on failed claim is zero.
111 // on successful claim is 1 << n, and on failed claim is zero.
121 // on successful claim is 1 << n, and on failed claim is zero.
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| /hal_rpi_pico-latest/src/rp2_common/hardware_clocks/include/hardware/ |
| D | clocks.h | 24 …* The clocks block provides independent clocks to on-chip and external components. It takes inputs…
29 * Please refer to the appropriate datasheet for more details on the RP-series clocks.
31 …* The clock source depends on which clock you are attempting to configure. The first table below s…
36 * On RP2040 the clock sources are:
49 …* The auxiliary clock sources available for use in the configure function depend on which clock is…
88 * On RP2350 the clock sources are:
101 …* The auxiliary clock sources available for use in the configure function depend on which clock is…
195 …TDIV1, System clock PLL post divider 1 setting, type=int, default=6 on RP2040 or 5 on RP2350, adva…
268 * See the tables in the description for details on the possible values for clock sources.
272 * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0
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| /hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/ |
| D | sio.h | 41 // 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0
53 // 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
58 // 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
63 // 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
73 // 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
78 // 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
83 // 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
93 // 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i
98 // 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i
103 // 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i
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| D | spi.h | 28 // Control register 0, SSPCR0 on page 3-4
37 // Control register 1, SSPCR1 on page 3-5
45 // Data register, SSPDR on page 3-6
50 // Status register, SSPSR on page 3-7
59 // Clock prescale register, SSPCPSR on page 3-8
64 // Interrupt mask set or clear register, SSPIMSC on page 3-9
72 // Raw interrupt status register, SSPRIS on page 3-10
80 // Masked interrupt status register, SSPMIS on page 3-11
88 // Interrupt clear register, SSPICR on page 3-11
94 // DMA control register, SSPDMACR on page 3-12
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| /hal_rpi_pico-latest/src/rp2_common/pico_unique_id/include/pico/ |
| D | unique_id.h | 22 * RP2040 does not have an on-board unique identifier (all instances of RP2040
38 * On boards using RP2350, the unique identifier is read from OTP memory on boot.
52 …* On an RP2040-based board, the unique identifier is retrieved from the external NOR flash device …
57 * On an RP2350-based board, the unique identifier is retrieved from OTP memory at boot.
71 …* On an RP2040-based board, the unique identifier is retrieved from the external NOR flash device …
76 * On an RP2350-based board, the unique identifier is retrieved from OTP memory at boot.
89 …* On an RP2040-based board, the unique identifier is retrieved from the external NOR flash device …
94 * On an RP2350-based board, the unique identifier is retrieved from OTP memory at boot.
|
| /hal_rpi_pico-latest/src/rp2_common/hardware_interp/include/hardware/ |
| D | interp.h | 42 …* Please refer to the appropriate RP-series microcontroller datasheet for more information on the …
74 * \param interp Interpolator on which to claim a lane. interp0 or interp1
84 * \param interp Interpolator on which to claim lanes. interp0 or interp1
92 * \param interp Interpolator on which to release a lane. interp0 or interp1
113 * \param interp Interpolator on which to release lanes. interp0 or interp1
121 * Sets the number of bits the accumulator is shifted before masking, on each iteration.
167 * Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation.
227 * Only present on INTERP1 on each core. If CLAMP mode is enabled:
242 * ORed into bits 29:28 of the lane result presented to the processor on the bus.
244 * No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
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| /hal_rpi_pico-latest/src/common/pico_time/include/pico/ |
| D | time.h | 24 …* e.g. timeouts, that relies on them) to work correctly, the hardware timer should not be modified…
213 …alling core to sleep. This is a lower powered sleep; waking and re-checking time on every processor
258 /*! \brief Helper method for blocking on a timeout
264 * This method can be used to implement a lower power polling loop waiting on
277 * // we are waiting on has happened
302 …* calls (except when the callback would happen before or during being set) the callback on the co…
307 * on core 0, and may be used by the method variants that take no alarm pool parameter.
361 * alarms or other functionality based on alarms when the alarm may have expired, as eventually
410 …* The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is cal…
413 * might want to create another if you want alarm callbacks on core 1 or require alarm pools of
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| /hal_rpi_pico-latest/src/rp2_common/hardware_xip_cache/include/hardware/ |
| D | xip_cache.h | 24 * The only valid cache maintenance operation on RP2040 is "invalidate", which tells the cache to
27 * on the external flash device, and could return stale data.
31 * On RP2350, the three types of operation are:
99 * flash_flush_cache() calls a ROM API which can have other effects on some platforms, like
100 * cleaning up the bootrom's QSPI GPIO setup on RP2040. Prefer this function for general cache
110 * Must be 4-byte-aligned on RP2040. Must be a aligned to the start of a cache line
111 * (XIP_CACHE_LINE_SIZE) on other platforms.
113 * \param size_bytes The number of bytes to invalidate. Must be a multiple of 4 bytes on RP2040.
114 * Must be a multiple of XIP_CACHE_LINE_SIZE on other platforms.
140 * On RP2040 this is a no-op, as the XIP cache is read-only. This is indicated by the
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| /hal_rpi_pico-latest/src/rp2350/hardware_structs/include/hardware/structs/ |
| D | spi.h | 28 // Control register 0, SSPCR0 on page 3-4
37 // Control register 1, SSPCR1 on page 3-5
45 // Data register, SSPDR on page 3-6
50 // Status register, SSPSR on page 3-7
59 // Clock prescale register, SSPCPSR on page 3-8
64 // Interrupt mask set or clear register, SSPIMSC on page 3-9
72 // Raw interrupt status register, SSPRIS on page 3-10
80 // Masked interrupt status register, SSPMIS on page 3-11
88 // Interrupt clear register, SSPICR on page 3-11
94 // DMA control register, SSPDMACR on page 3-12
|
| D | sio.h | 40 // Input value on GPIO32
41 …// 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 p…
42 // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin
43 // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin
44 // 0x02000000 [25] USB_DM (0) Input value on USB D- pin
45 // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin
46 // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32
68 // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
83 // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
98 // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
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| /hal_rpi_pico-latest/src/rp2_common/pico_bootrom/include/pico/ |
| D | bootrom.h | 65 // translation). Need to take care using this on the boot path, as the QMI may not yet have been
72 // QMI_ATRANSx if necessary, and checking flash permissions based on the resident partition table
74 // flash storage address, depending on the ASPACE given in `flags`.
111 /*! \brief Return a bootrom lookup code based on two ASCII characters
147 * \param table an IN/OUT array, elements are codes on input, function pointers on success.
201 // on RISC-V the code (a jmp) is actually embedded in the table in rom_func_lookup_inline()
205 // on ARM the function pointer is stored in the table, so we dereference it in rom_func_lookup_inline()
255 * \param usb_activity_gpio_pin_active_low Activity GPIO is active low (ignored on RP2040)
266 …* On RP2350 if a secondary flash chip select GPIO has been configured via OTP OTP_DATA_FLASH_DEVIN…
281 …* On RP2040, first set up the SSI for serial-mode operations, then issue the fixed XIP exit sequen…
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| /hal_rpi_pico-latest/src/rp2_common/pico_runtime_init/include/pico/ |
| D | runtime_init.h | 53 // must have no dependency on any other initialization code
57 // Reset of global bootrom state (can be skipped if boot path was via bootrom); not used on RP2040
59 …ime_init_bootrom_reset` function during runtime init, type=bool, default=1 on RP2040, group=pico_r…
60 …lementation of `runtime_init_bootrom_reset` function, type=bool, default=1 on RP2040, group=pico_r…
83 // Non-boot core eset of bootrom state, not needed if only using core 0 not used on RP2040
89 …er_core_bootrom_reset` function during per-core init, type=bool, default=1 on RP2040, group=pico_r…
90 …on of `runtime_init_per_core_bootrom_reset` function, type=bool, default=1 on RP2040, group=pico_r…
111 …core_h3_irq_registers` function during per-core init, type=bool, default=1 on non RISC-V, group=pi…
130 …time_init_early_resets` function during runtime init, type=bool, default=1 on RP2040, group=pico_r…
131 …plementation of `runtime_init_early_resets` function, type=bool, default=1 on RP2040, group=pico_r…
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| /hal_rpi_pico-latest/src/rp2_common/pico_flash/ |
| D | flash.c | 29 // 1. No use of core 1 - we just want to disable IRQs and not wait on core 1 to acquiesce
31 // 3. FreeRTOS on core 0, no use of core 1 - we just want to disable IRQs
32 // 4. FreeRTOS SMP on both cores - we need to schedule a high priority task on the other core to di…
33 // 5. FreeRTOS on one core, but application is using the other core. ** WE CANNOT SUPPORT THIS TODA…
142 … // Note that whilst taskENTER_CRITICAL sounds promising (and on non SMP it disabled IRQs), on SMP in default_enter_safe_zone_timeout_ms()
144 …// Therefore, we must do our own handshake which starts a task on the other core and have it disab… in default_enter_safe_zone_timeout_ms()
146 // create at low priority on other core in default_enter_safe_zone_timeout_ms()
193 // we always want to disable IRQs on our core in default_enter_safe_zone_timeout_ms()
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| /hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/ |
| D | LICENSE.txt | 41 form, that is based on (or derived from) the Work and for which the
52 or by an individual or Legal Entity authorized to submit on behalf of
56 communication on electronic mailing lists, source code control systems,
57 and issue tracking systems that are managed by, or on behalf of, the
63 on behalf of whom a Contribution has been received by Licensor and
145 Contributor provides its Contributions) on an "AS IS" BASIS,
170 on Your own behalf and on Your sole responsibility, not on behalf
185 file or class name and description of purpose be included on the
198 distributed under the License is distributed on an "AS IS" BASIS,
|
| /hal_rpi_pico-latest/src/rp2_common/hardware_gpio/include/hardware/ |
| D | gpio.h | 51 …* The number of GPIO pins available depends on the package. There are 30 user GPIOs in bank 0 in t…
56 * Converter (ADC). The allocation of GPIO pins to the ADC depends on the packaging.
61 …* Each GPIO can be controlled directly by software running on the processors, or by a number of ot…
64 * are available on all pins.
66 …tion selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be selected on
68 * GPIO inputs. Please refer to the datasheet for more information on GPIO function select.
73 * On RP2040 the function selects are:
109 * On RP2350 the function selects are:
282 /*! \brief Select up and down pulls on specific GPIO
286 * \param up If true set a pull up on the GPIO
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