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/hal_espressif-latest/components/driver/spi/include/driver/
Dspi_common.h60 …COMMON_BUSFLAG_MOSI (1<<5) ///< Check existing of MOSI pin. Or indicates MOSI line in…
61 #define SPICOMMON_BUSFLAG_DUAL (1<<6) ///< Check MOSI and MISO pins can output. Or ind…
63 …SPICOMMON_BUSFLAG_DUAL|SPICOMMON_BUSFLAG_WPHD) ///< Check existing of MOSI/MISO/WP/HD pins as …
65 …SPICOMMON_BUSFLAG_QUAD|SPICOMMON_BUSFLAG_IO4_IO7) ///< Check existing of MOSI/MISO/WP/HD/SPIIO4/S…
Dspi_slave.h74 const void *tx_buffer; ///< Pointer to transmit buffer, or NULL for no MOSI phase
Dspi_master.h39 #define SPI_DEVICE_3WIRE (1<<2) ///< Use MOSI (=spid) for both sending and recei…
140 const void *tx_buffer; ///< Pointer to transmit buffer, or NULL for no MOSI phase
/hal_espressif-latest/tools/esptool_py/docs/en/advanced-topics/
Dspi-flash-modes.rst40 * Master Out Slave In (MOSI)
46 … from the device to the host using the MISO pin and from the host to the device using the MOSI pin.
53 To improve performance, SPI flash manufacturers introduced "Dual SPI". In Dual SPI modes, the MOSI …
55 … flash chip via normal SPI, but then the host reads the data via both the MOSI & MISO pins simulta…
58 …a normal SPI, but then the address is sent to the flash chip via both the MOSI & MISO pins with tw…
/hal_espressif-latest/components/esp_rom/include/esp32s2/rom/
Dopi_flash.h172 * @param mosi_data data buffer to be sent in mosi field
173 * @param mosi_bit_len bit length of data buffer to be sent in mosi field
/hal_espressif-latest/zephyr/port/pincfgs/
Desp32s2.yml52 mosi:
81 mosi:
Desp32c2.yml48 mosi:
Desp32c3.yml48 mosi:
Desp32c6.yml53 mosi:
Desp32.yml67 mosi:
87 mosi:
Desp32s3.yml139 mosi:
168 mosi:
/hal_espressif-latest/components/bootloader_support/bootloader_flash/include/
Dbootloader_flash_priv.h174 * @param mosi_data MOSI data to send
175 * @param mosi_len Length of MOSI data, in bits
/hal_espressif-latest/components/esp_rom/include/esp32s3/rom/
Dopi_flash.h210 * @param mosi_data data buffer to be sent in mosi field
211 * @param mosi_bit_len bit length of data buffer to be sent in mosi field
/hal_espressif-latest/components/soc/esp32/include/soc/
Dspi_struct.h63 …uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: L…
92 …uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1:…
93 …uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/
116 … /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
119 …uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: b…
124 … /*Set the bit to enable 3-line half duplex communication mosi and miso signals sh…
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dspi_struct.h41 …uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: hi…
46 …uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: L…
72 … : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. …
79 … : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals sh…
/hal_espressif-latest/components/hal/
Dspi_slave_hal_iram.c75 //SPI Slave mode on ESP32 requires MOSI/MISO enable in spi_slave_hal_prepare_data()
/hal_espressif-latest/components/driver/spi/gpspi/
Dspi_common.c550 SPI_CHECK_PIN(bus_config->mosi_io_num, "mosi", mosi_need_output); in spicommon_bus_initialize_io()
556 //set flags for DUAL mode according to output-capability of MOSI and MISO pins. in spicommon_bus_initialize_io()
579 ESP_LOGE(SPI_TAG, "mosi pin required."); in spicommon_bus_initialize_io()
585 ESP_LOGE(SPI_TAG, "not both mosi and miso output capable"); in spicommon_bus_initialize_io()
Dspi_master.c788 …| !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", … in check_trans_valid()
792 …_enabled || !rx_enabled, "SPI half duplex mode is not supported when both MOSI and MISO phases are… in check_trans_valid()
793 …| !trans_desc->rxlength, "SPI half duplex mode is not supported when both MOSI and MISO phases are… in check_trans_valid()
795 //MOSI phase is skipped only when both tx_buffer and SPI_TRANS_USE_TXDATA are not set. in check_trans_valid()
796 …_buffer should be NULL and SPI_TRANS_USE_TXDATA should be cleared to skip MOSI phase.", ESP_ERR_IN… in check_trans_valid()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dspi_struct.h44 …uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: hi…
49 …uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: L…
75 … : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. …
82 … : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals sh…
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dspi_struct.h52 …uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: hi…
57 …uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: L…
83 … : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. …
90 … : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals sh…
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_struct.h43 …uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high…
48 …uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB…
95 …1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. …
97 …uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big…
102 …; /*Set the bit to enable 3-line half duplex communication mosi and miso signals sh…
/hal_espressif-latest/components/driver/include/esp_private/
Dspi_common_internal.h167 …* Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capabili…
168 …* - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so th…
177 * CLK/MISO/MOSI connected.
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dspi_ll.h192 * Determine and unify the default level of mosi line when bus free
198 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
572 * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
778 * Set the mosi delay after the output edge to the signal. (Preview)
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dspi_ll.h194 * Determine and unify the default level of mosi line when bus free
200 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
574 * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
768 * Set the mosi delay after the output edge to the signal. (Preview)
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dspi_ll.h190 * Determine and unify the default level of mosi line when bus free
196 hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state in spi_ll_set_mosi_free_level()
570 * SIO is a mode which MOSI and MISO share a line. The device MUST work in half-duplexmode.
764 * Set the mosi delay after the output edge to the signal. (Preview)

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