| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig.soc | 20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
21 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins.
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
28 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
36 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins.
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
43 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins,
50 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
51 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins,
[all …]
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/ |
| D | Kconfig.soc | 20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
21 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins.
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
28 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
36 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins.
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| /Zephyr-latest/dts/bindings/serial/ |
| D | uart-controller-pin-inversion.yaml | 10 Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and
15 Invert the binary logic of rx pin. When enabled, physical logic levels are inverted and
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| /Zephyr-latest/drivers/regulator/ |
| D | Kconfig.cp9314 | 1 # Copyright (c) 2023 Cirrus Logic, Inc.
9 Enable the Cirrus Logic CP9314 Switched Cap Converter
17 Init priority for the Cirrus Logic CP9314 Switched Cap
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| /Zephyr-latest/dts/bindings/misc/ |
| D | nxp,s32-lcu.yaml | 5 Logic control Unit for NXP S32 SoCs.
8 using a programmable logic function to create output waveforms
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| /Zephyr-latest/tests/bluetooth/df/connectionless_cte_tx/src/ |
| D | test_set_cl_cte_tx_enable.c | 72 /* test logic */ in ZTEST()
91 /* test logic */ in ZTEST()
111 /* test logic */ in ZTEST()
132 /* test logic */ in ZTEST()
152 /* test logic */ in ZTEST()
173 /* test logic */ in ZTEST()
195 /* test logic */ in ZTEST()
215 /* test logic */ in ZTEST()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.cavs | 7 bool "CAVS Interrupt Logic"
43 Cavs Interrupt Logic initialization priority.
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| /Zephyr-latest/drivers/sensor/tdk/icm42688/ |
| D | icm42688_spi.h | 16 * this functions wraps all logic necessary to write to any of the ICM42688 registers, regardless
29 * this functions wraps all logic necessary to update any of the ICM42688 registers, regardless
44 * this functions wraps all logic necessary to read from any of the ICM42688 registers, regardless
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ |
| D | adsp_timestamp.h | 22 * @brief Perform timestamping process using DfTTS logic.
24 * @param tsctrl Value to be applied to DfTSCTRL register to control timestamping logic
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| /Zephyr-latest/include/zephyr/dt-bindings/sensor/ |
| D | qdec_nxp_s32.h | 7 /* Logic Trigger Numbers. See Trgmux_Ip_Init_PBcfg.h */
8 #define TRGMUX_LOGIC_GROUP_0_TRIGGER_0 (0) /* Logic Trigger 0 */
9 #define TRGMUX_LOGIC_GROUP_0_TRIGGER_1 (1) /* Logic Trigger 1 */
10 #define TRGMUX_LOGIC_GROUP_1_TRIGGER_0 (2) /* Logic Trigger 2 */
11 #define TRGMUX_LOGIC_GROUP_1_TRIGGER_1 (3) /* Logic Trigger 3 */
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| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da.qpf | 4 # Your use of Altera Corporation's design tools, logic functions
5 # and other software and tools, and its AMPP partner logic
13 # that your use is for the sole purpose of programming logic
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | ti,tca9538.yaml | 37 Interrupt mask register is set to logic 1 by default without
38 enabling interrupts. Setting corresponding mask bits to logic
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| /Zephyr-latest/include/zephyr/platform/ |
| D | hooks.h | 14 * zephyr architecture and initialization code and the SoC and board specific logic
18 * soc and board specific logic to OS internal logic. These should never be accessed
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| /Zephyr-latest/drivers/input/ |
| D | Kconfig.sbus | 45 sets the threshold to interperted the analogue value as an logic 1
52 sets the threshold to interperted the analogue value as an logic 0
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | nxp,s32-qdec.yaml | 62 This gives the logic triggers configuration of TRGMUX module.
63 It contains 3 values for each of the 4 logic triggers used:
64 logic trigger number, output, input.
107 Logic Cell number used inside an LCU instance.
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| /Zephyr-latest/tests/cmake/snippets/ |
| D | Kconfig | 10 # Snippet test types used by the test implementation to steer the test logic
42 # Test values set by the snippet config overlays and tested by the test logic
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| /Zephyr-latest/arch/arm64/core/ |
| D | macro_priv.inc | 25 * Get CPU logic id by looking up cpu_node_list
28 * xreg1: logic id (0 ~ CONFIG_MP_MAX_NUM_CPUS - 1)
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| /Zephyr-latest/modules/openthread/platform/ |
| D | openthread-core-zephyr-config.h | 23 * The assert is managed by platform defined logic when this flag is set.
89 * Define to 1 to enable software ACK timeout logic.
99 * Define to 1 to enable software retransmission logic.
109 * Define to 1 if you want to enable software CSMA-CA backoff logic.
168 * Define to 1 to enable software transmission target time logic.
179 * Define to 1 to enable software reception target time logic.
344 * Set to 1 to enable software transmission security logic.
434 * The message pool is managed by platform defined logic.
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| /Zephyr-latest/doc/hardware/peripherals/can/ |
| D | transceiver.rst | 13 A CAN transceiver is an external device that converts the logic level signals
18 These wires use the logic levels whereas the bus-level is interpreted
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| /Zephyr-latest/tests/kernel/timer/timer_behavior/pytest/ |
| D | saleae_logic2.py | 5 # Sample code showing an external tool Python module helper for Saleae Logic 2
6 # compatible logic analyzer.
7 # To use it, the Saleae Logic 2 Automation server must be enabled. For more
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | macro_priv.inc | 22 * Get CPU logic id by looking up cpu_node_list
25 * reg1: logic id (0 ~ CONFIG_MP_MAX_NUM_CPUS - 1)
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| /Zephyr-latest/tests/drivers/charger/sbs_charger/boards/ |
| D | emulated_board.conf | 1 # Copyright (c) 2023 Cirrus Logic, Inc.
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| D | qemu_cortex_a53.conf | 1 # Copyright (c) 2023 Cirrus Logic, Inc.
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| /Zephyr-latest/tests/drivers/build_all/charger/src/ |
| D | main.c | 2 * Copyright (c) 2023 Cirrus Logic, Inc.
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| /Zephyr-latest/tests/drivers/build_all/haptics/src/ |
| D | main.c | 2 * Copyright (c) 2024 Cirrus Logic, Inc.
|
