| /hal_espressif-latest/tools/idf_monitor/idf_monitor_base/ |
| D | serial_reader.py | 47 self.serial.dtr = low # Non reset state
49 self.serial.dtr = self.serial.dtr # usbser.sys workaround
53 self.serial.dtr = high # Set dtr to reset state (affected by rts)
54 self.serial.rts = low # Set rts/dtr to the reset state
55 self.serial.dtr = self.serial.dtr # usbser.sys workaround
60 self.serial.rts = high # Set rts/dtr to the working state
61 self.serial.dtr = self.serial.dtr # usbser.sys workaround
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| D | serial_handler.py | 167 self.serial_instance.setDTR(self.serial_instance.dtr) # usbser.sys workaround
170 self.serial_instance.setDTR(self.serial_instance.dtr) # usbser.sys workaround
186 self.serial_instance.setDTR(self.serial_instance.dtr) # usbser.sys workaround
190 self.serial_instance.setDTR(self.serial_instance.dtr) # usbser.sys workaround
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| /hal_espressif-latest/tools/esptool_py/esptool/ |
| D | reset.py | 53 "WARNING: Chip was NOT reset. Setting RTS/DTR lines is not "
73 # generate a dummy change to DTR so that the set-control-line-state
74 # request is sent with the updated RTS state and the same DTR state
75 self.port.setDTR(self.port.dtr)
77 def _setDTRandRTS(self, dtr=False, rts=False): argument
81 if dtr:
94 Classic reset sequence, sets DTR and RTS lines sequentially.
110 which allows setting DTR and RTS lines at the same time.
139 self._setRTS(True) # RTS set as Windows only propagates DTR on RTS setting
159 # to be able to handle further DTR/RTS transitions
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| /hal_espressif-latest/components/esp_hw_support/port/esp32s3/ |
| D | mspi_timing_tuning_configs.h | 87 * define the STR/DTR mode here for selecting the core clock:
88 * @note If either Flash or PSRAM, or both of them are set to DTR mode, then we use DIV 2
97 //FLASH 80M DTR
102 //FLASH 120M DTR
117 //PSRAM 80M DTR
134 #endif //PSRAM 120M DTR
192 //FLASH: core clock 160M, module clock 40M, DTR mode
197 //FLASH: core clock 160M, module clock 80M, DTR mode
202 //FLASH: core clock 240M, module clock 120M, DTR mode
222 //PSRAM: core clock 80M, module clock 40M, DTR mode
[all …]
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| /hal_espressif-latest/tools/esptool_py/docs/en/esptool/ |
| D | advanced-options.rst | 22 …* ``--before default_reset`` is the default, which uses DTR & RTS serial control lines (see :ref:`…
23 …DTR/RTS control signal assignments and just start sending a serial synchronisation command to the …
24 …* ``--before no_reset_no_sync`` will skip DTR/RTS control signal assignments and skip also the ser…
34 …* ``--after hard_reset`` is the default. The DTR serial control line is used to reset the chip int…
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| D | remote-serial-ports.rst | 10 Custom baud rates and DTR/RTS automatic resetting are supported over the RFC2217 protocol, the same…
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| /hal_espressif-latest/components/esp_rom/include/esp32s2/rom/ |
| D | opi_flash.h | 147 * @brief Set data swap mode in DTR(DDR) mode
149 * @param wr_swap to decide whether to swap fifo data in dtr write operation
150 * @param rd_swap to decide whether to swap fifo data in dtr read operation
156 * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
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| /hal_espressif-latest/components/spi_flash/ |
| D | spi_flash_chip_mxic_opi.c | 90 …/* Under STR mode, one byte occupies one single clock. While under DTR mode, one byte occupies hal… in spi_flash_chip_mxic_opi_get_data_length_zoom()
91 …on needs 3 clock dummy, host send 3 dummy bytes under STR mode, while 6 dummy bytes under DTR mode. in spi_flash_chip_mxic_opi_get_data_length_zoom()
113 // Adjust the id_buf in DTR mode, because in DTR mode, the data back in STR rule. in spi_flash_chip_mxic_opi_read_id()
149 // For DTR mode, RDSR result like [SR1, SR1], just keeping one SR1. in spi_flash_chip_mxic_opi_read_reg()
330 // For DTR mode, RDSR result like [CR1, CR1], just keeping one CR1. in spi_flash_chip_mxic_opi_get_io_mode()
360 …on should only be called after opi mode initialization. So, only configure for OPI-STR/OPI-DTR mode
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| /hal_espressif-latest/tools/esptool_py/esp_rfc2217_server/ |
| D | __init__.py | 75 ser.dtr = False
100 ser.dtr = True
109 ser.dtr = False
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| D | esp_port_manager.py | 47 self.serial.dtr = False
81 The reset logic is used from esptool.py because the RTS and DTR signals
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| /hal_espressif-latest/components/esp_rom/include/esp32s3/rom/ |
| D | opi_flash.h | 187 * @brief Set data swap mode in DTR(DDR) mode
189 * @param wr_swap to decide whether to swap fifo data in dtr write operation
190 * @param rd_swap to decide whether to swap fifo data in dtr read operation
196 * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
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| /hal_espressif-latest/tools/esptool_py/docs/en/advanced-topics/ |
| D | boot-mode-selection.rst | 123 …DTR`` and ``RTS`` control lines of the USB to serial converter chip, i.e., FTDI, CP210x, or CH340x…
127 …When developing ``esptool.py``, keep in mind ``DTR`` and ``RTS`` are active low signals, i.e., ``T…
131 - The **Micro USB 5V & USB-UART** section shows the ``DTR`` and ``RTS`` control lines of the USB t…
132 - Some OS and/or drivers may activate ``RTS`` and or ``DTR`` automatically when opening the serial…
133 …itry is implemented in order to avoid this problem - if both ``RTS`` and ``DTR`` are asserted toge…
147 - DTR
155 - Your hardware does not have the ``DTR`` and ``RTS`` lines connected to ``{IDF_TARGET_STRAP_BOOT_G…
156 - The ``DTR`` and ``RTS`` lines are configured differently
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| /hal_espressif-latest/zephyr/port/pincfgs/ |
| D | esp32c2.yml | 17 dtr:
37 dtr:
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| D | esp32c3.yml | 17 dtr:
37 dtr:
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| D | esp32c6.yml | 22 dtr:
42 dtr:
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| D | esp32s2.yml | 21 dtr:
41 dtr:
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| /hal_espressif-latest/components/esp_system/port/ |
| D | usb_console.c | 145 uint32_t rts, dtr; in esp_usb_console_cdc_acm_cb() local
147 cdc_acm_line_ctrl_get(dev, LINE_CTRL_DTR, &dtr); in esp_usb_console_cdc_acm_cb()
149 if (dtr) { in esp_usb_console_cdc_acm_cb()
286 /* Set callback for handling DTR/RTS lines and TX/RX events */ in esp_usb_console_init()
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| /hal_espressif-latest/tools/esptool_py/flasher_stub/include/ |
| D | stub_io.h | 48 * No-op for UART, handles DTR/RTS reset for USB CDC.
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| /hal_espressif-latest/tools/esptool_py/ |
| D | esp_rfc2217_server.py | 18 # It uses a custom PortManager to properly apply the RTS & DTR signals
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| /hal_espressif-latest/components/spi_flash/include/spi_flash/ |
| D | spi_flash_defs.h | 24 #define CMD_8DTRD 0xEE /* MXIC-specific, 8 I/O DTR read */
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| /hal_espressif-latest/components/spi_flash/esp32s3/ |
| D | spi_flash_oct_flash_init.c | 112 // 0x00: SPI; 0x01: STR OPI; 0x02: DTR OPI
203 // STR/DTR specific setting in s_flash_init_mxic()
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| /hal_espressif-latest/components/hal/include/hal/ |
| D | spi_flash_types.h | 29 #define SPI_FLASH_TRANS_FLAG_BYTE_SWAP BIT(2) ///< Used for DTR mode, to swap the bytes of a …
67 SPI_FLASH_OPI_DTR,///< Only support on OPI flash, flash read and write under DTR mode
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | spi_struct.h | 133 …en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SP…
134 … : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas…
135 … : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including mas…
136 … : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including mas…
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | spi_struct.h | 141 …en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SP…
142 … : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas…
143 … : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including mas…
144 … : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including mas…
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| /hal_espressif-latest/components/soc/esp32c3/include/soc/ |
| D | uart_struct.h | 150 …rn: 1; /*This bit represents the level of the internal uart dtr signal.*/
163 … 1; /*This register is used to configure the software dtr signal which is use…
180 … dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/
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