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/Zephyr-latest/dts/bindings/pwm/
Draspberrypi,pico-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
18 type: int
20 The integral part of the divider for pwm slice 0.
22 as the integer part of the divider.
26 divider-frac-0:
27 type: int
29 The fractional part of the divider for pwm slice 0.
[all …]
Despressif,esp32-mcpwm.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Each MCPWM peripheral has one clock divider (prescaler), three PWM timers, three PWM operators,
25 Channel 0 -> Timer 0, Operator 0, output PWM0A
26 Channel 1 -> Timer 0, Operator 0, output PWM0B
27 Channel 2 -> Timer 1, Operator 1, output PWM1A
28 Channel 3 -> Timer 1, Operator 1, output PWM1B
29 Channel 4 -> Timer 2, Operator 2, output PWM2A
30 Channel 5 -> Timer 2, Operator 2, output PWM2B
31 Channel 6 -> Capture 0
32 Channel 7 -> Capture 1
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-auxpll.yaml2 # SPDX-License-Identifier: Apache-2.0
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
23 - nordic-nrf-ficr-client.yaml
[all …]
Dnxp,kinetis-mcg.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 type: int
19 enum: [0, 1, 2, 3, 4, 5, 6, 7]
21 Internal Reference Clock Divider.
25 type: int
26 enum: [0, 1, 2, 3, 4, 5, 6, 7]
28 Second Low-frequency Internal Reference Clock Divider.
[all …]
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
Dst,stm32c0-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
21 compatible: "st,stm32c0-hsi-clock"
[all …]
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
18 type: int
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
13 #define LPC11U6X_SYS_AHB_CLK_CTRL_GPIO (1 << 6)
47 #define LPC11U6X_PRESET_CTRL_USART2 (1 << 6)
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud
87 * rate generator clock divider
92 volatile uint32_t usb_clk_div; /* USB clock divider */
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Dclock_control_r8a779f0_cpg_mssr.c7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
82 static int r8a779f0_cpg_enable_disable_core(const struct device *dev, in r8a779f0_cpg_enable_disable_core()
85 int ret = 0; in r8a779f0_cpg_enable_disable_core()
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
100 ret = -ENOTSUP; in r8a779f0_cpg_enable_disable_core()
105 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a779f0_cpg_enable_disable_core()
[all …]
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
244 static int litex_clk_wait(uint32_t reg) in litex_clk_wait()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
262 return -ETIME; in litex_clk_wait()
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/Zephyr-latest/dts/bindings/tcpc/
Dst,stm32-ucpd.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ST STM32 family USB Type-C / Power Delivery. The default values were
8 compatible: "st,stm32-ucpd"
10 include: [base.yaml, pinctrl-device.yaml]
22 psc-ucpdclk:
24 type: int
26 - 1
27 - 2
28 - 4
29 - 8
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/Zephyr-latest/dts/bindings/can/
Datmel,sam-can.yaml3 compatible: "atmel,sam-can"
6 - name: bosch,m_can-base.yaml
7 - name: pinctrl-device.yaml
16 reg-names:
17 type: string-array
25 interrupt-names:
31 divider:
32 type: int
35 - 6
36 - 12
[all …]
Dst,stm32h7-fdcan.yaml3 compatible: "st,stm32h7-fdcan"
5 include: ["bosch,m_can-base.yaml", "pinctrl-device.yaml"]
17 interrupt-names:
20 clk-divider:
21 type: int
23 - 1
24 - 2
25 - 4
26 - 6
27 - 8
[all …]
Dst,stm32-fdcan.yaml3 compatible: "st,stm32-fdcan"
5 include: ["bosch,m_can-base.yaml", "pinctrl-device.yaml"]
14 interrupt-names:
20 clk-divider:
21 type: int
23 - 1
24 - 2
25 - 4
26 - 6
27 - 8
[all …]
/Zephyr-latest/drivers/sensor/st/lis3mdl/
Dlis3mdl.c4 * SPDX-License-Identifier: Apache-2.0
22 uint16_t divider) in lis3mdl_convert() argument
24 /* val = raw_val / divider */ in lis3mdl_convert()
25 val->val1 = raw_val / divider; in lis3mdl_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in lis3mdl_convert()
29 static int lis3mdl_channel_get(const struct device *dev, in lis3mdl_channel_get()
33 struct lis3mdl_data *drv_data = dev->data; in lis3mdl_channel_get()
37 lis3mdl_convert(val, drv_data->x_sample, in lis3mdl_channel_get()
39 lis3mdl_convert(val + 1, drv_data->y_sample, in lis3mdl_channel_get()
41 lis3mdl_convert(val + 2, drv_data->z_sample, in lis3mdl_channel_get()
[all …]
/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
28 type: int
31 Clock divider value for the global prescaler. Could be in range [1 ... 256]
33 internal-cnt:
34 type: int
39 child-binding:
40 child-binding:
[all …]
Drenesas,ra-agt.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-agt"
15 type: int
18 renesas,count-source:
23 - "AGT_CLOCK_PCLKB"
24 - "AGT_CLOCK_LOCO"
28 AGT clock divider for LOCO and SUBCLOCK. timer clock = (clock-source / (1 << prescaler))
31 type: int
34 - 0
35 - 1
[all …]
/Zephyr-latest/drivers/serial/
Duart_b91.c4 * SPDX-License-Identifier: Apache-2.0
22 ((const struct uart_b91_config *)dev->config)->uart_addr)
41 #define UART_RX_RESET_BIT BIT(6)
85 UART_RX_IRQ_MASK = BIT(6),
111 return (uart->bufcnt & FLD_UART_TX_BUF_CNT) >> FLD_UART_TX_BUF_CNT_OFFSET; in uart_b91_get_tx_bufcnt()
117 return (uart->bufcnt & FLD_UART_RX_BUF_CNT) >> FLD_UART_RX_BUF_CNT_OFFSET; in uart_b91_get_rx_bufcnt()
131 for (i = 5; i * i < n; i += 6) { in uart_b91_is_prime()
142 uint16_t *divider, uint8_t *bwpc) in uart_b91_cal_div_and_bwpc() argument
151 primeDec = 10 * pclk / baudrate - 10 * primeInt; in uart_b91_cal_div_and_bwpc()
158 primeInt -= 1; in uart_b91_cal_div_and_bwpc()
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dadi,adltc2990.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: [sensor-device.yaml, i2c-device.yaml]
12 temperature-format:
13 type: int
19 - 0
20 - 1
22 acquistion-format:
23 type: int
29 - 0
30 - 1
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_iwdg_stm32.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
50 * maximum 6 cycles (48 ms at 32 kHz) for register update.
52 #define IWDG_SR_UPDATE_TIMEOUT (6U * IWDG_PRESCALER_MAX * \
66 uint16_t divider = 4U; in iwdg_stm32_convert_timeout() local
72 while ((ticks / divider) > IWDG_RELOAD_MAX) { in iwdg_stm32_convert_timeout()
74 divider = 4U << shift; in iwdg_stm32_convert_timeout()
82 *reload = (uint32_t)(ticks / divider) - 1U; in iwdg_stm32_convert_timeout()
85 static int iwdg_stm32_setup(const struct device *dev, uint8_t options) in iwdg_stm32_setup()
110 return -ENOTSUP; in iwdg_stm32_setup()
[all …]
/Zephyr-latest/dts/bindings/display/
Dsolomon,ssd1327fb.yaml1 # Copyright (c) 2024, Savoir-faire Linux
2 # SPDX-License-Identifier: Apache-2.0
4 description: SSD1327 128x128 dot-matrix display controller on MIPI_DBI bus
6 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
11 oscillator-freq:
12 type: int
14 description: Front clock divider / oscillator frequency
16 display-offset:
17 type: int
21 start-line:
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/Zephyr-latest/dts/bindings/video/
Dovti,ov2640.yaml2 # SPDX-License-Identifier: Apache-2.0
9 reset-gpios:
10 type: phandle-array
13 reset. The sensor receives this as an active-low signal.
15 clock-rate-control:
16 type: int
24 Bit[6] Reserved
25 Bit[5:0] Clock divider.
29 include: i2c-device.yaml
/Zephyr-latest/drivers/sensor/honeywell/hmc5883l/
Dhmc5883l.c4 * SPDX-License-Identifier: Apache-2.0
22 uint16_t divider) in hmc5883l_convert() argument
24 /* val = raw_val / divider */ in hmc5883l_convert()
25 val->val1 = raw_val / divider; in hmc5883l_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in hmc5883l_convert()
29 static int hmc5883l_channel_get(const struct device *dev, in hmc5883l_channel_get()
33 struct hmc5883l_data *drv_data = dev->data; in hmc5883l_channel_get()
36 hmc5883l_convert(val, drv_data->x_sample, in hmc5883l_channel_get()
37 hmc5883l_gain[drv_data->gain_idx]); in hmc5883l_channel_get()
39 hmc5883l_convert(val, drv_data->y_sample, in hmc5883l_channel_get()
[all …]
/Zephyr-latest/include/zephyr/drivers/can/
Dcan_sja1000.h4 * SPDX-License-Identifier: Apache-2.0
27 #define CAN_SJA1000_OCR_OCTN1 BIT(6)
38 * @name SJA1000 Clock Divider Register (CDR) bits
45 #define CAN_SJA1000_CDR_CBP BIT(6)
55 #define CAN_SJA1000_CDR_CD_DIV14 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 6U)
84 * @brief SJA1000 driver front-end callback for writing a register value
93 * @brief SJA1000 driver front-end callback for reading a register value
121 * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value
143 * @param _cdr Initial SJA1000 Clock Divider Register (CDR) value
189 int can_sja1000_set_timing(const struct device *dev, const struct can_timing *timing);
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,lpc11u6x-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
4 compatible: "nxp,lpc11u6x-pinctrl"
7 - name: base.yaml
8 - name: nxp,lpc-iocon-pinctrl.yaml
9 child-binding:
10 child-binding:
11 property-allowlist:
12 - pinmux
13 - nxp,invert
14 - nxp,analog-mode
[all …]

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