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/Zephyr-Core-3.6.0/drivers/usb/device/
DKconfig7 bool "USB device controller drivers"
9 Enable USB device controller drivers.
14 bool "USB device controller supports high speed"
16 USB device controller supports high speed.
21 USB device controller supports remote wakeup feature.
24 bool "Designware USB Device Controller Driver"
28 Designware USB Device Controller Driver.
31 bool "DesignWare Controller and PHY support for USB specification 2.0"
37 bool "USB device controller driver for Raspberry Pi Pico devices"
47 bool "USB device controller driver for STM32 devices"
[all …]
/Zephyr-Core-3.6.0/dts/arm/cypress/
Dpsoc6_cm0.dtsi29 intmux_ch0: interrupt-controller@0 {
33 interrupt-controller;
37 intmux_ch1: interrupt-controller@1 {
41 interrupt-controller;
45 intmux_ch2: interrupt-controller@2 {
49 interrupt-controller;
53 intmux_ch3: interrupt-controller@3 {
57 interrupt-controller;
61 intmux_ch4: interrupt-controller@4 {
65 interrupt-controller;
[all …]
/Zephyr-Core-3.6.0/tests/bluetooth/controller/uut/
DCMakeLists.txt10 ${ZEPHYR_BASE}/subsys/bluetooth/controller/util/mem.c
11 ${ZEPHYR_BASE}/subsys/bluetooth/controller/util/memq.c
12 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_tx_queue.c
13 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_conn.c
14 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ll_feat.c
15 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_llcp_conn_upd.c
16 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_llcp_cc.c
17 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_llcp_pdu.c
18 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_llcp_remote.c
19 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/ull_llcp_local.c
[all …]
/Zephyr-Core-3.6.0/drivers/interrupt_controller/
DKconfig.dw5 bool "Designware Interrupt Controller for ACE"
10 Designware Interrupt Controller used by ACE.
13 bool "Designware Interrupt Controller"
18 Designware Interrupt Controller can be used as a 2nd level interrupt
19 controller which combines several sources of interrupt into one line
20 that is then routed to the 1st level interrupt controller.
26 string "Name for Designware Interrupt Controller"
29 Give a name for the instance of Designware Interrupt Controller
36 the ISRs for Designware Interrupt Controller are assigned.
39 int "Init priority for DW interrupt controller"
[all …]
DKconfig1 # interrupt controller configuration options
6 menu "Interrupt controller drivers"
20 bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
24 Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU.
27 bool "VexRiscv LiteX Interrupt controller"
34 bool "GRLIB IRQMP interrupt controller"
41 int "Interrupt controller init priority"
44 Interrupt controller device initialization priority.
49 int "XEX GIRQ Interrupt controller init priority"
52 XEC GIRQ Interrupt controller device initialization priority.
DKconfig.nxp_s321 # Configuration for NXP S32 external interrupt controller
7 bool "External interrupt controller driver for NXP S32 MCUs"
12 External interrupt controller driver for NXP S32 MCUs
15 bool "Wake-up Unit interrupt controller driver for NXP S32 MCUs"
20 Wake-up Unit interrupt controller driver for NXP S32 MCUs
/Zephyr-Core-3.6.0/drivers/reset/
DKconfig1 # Reset Controller driver configuration options
7 # Reset Controller options
10 bool "Reset Controller drivers"
12 Reset Controller drivers. Reset node represents a region containing
13 information about reset controller device. The typical use-case is
15 controller node together with some reset information.
20 int "Reset Controller driver init priority"
23 This option controls the priority of the reset controller device
28 comment "Reset Controller Drivers"
/Zephyr-Core-3.6.0/dts/bindings/gpio/
Dnxp,s32-gpio.yaml5 NXP S32 GPIO controller.
7 The GPIO controller provides the option to route external input pad interrupts
8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10 SIUL2 EIRQ interrupt controller.
12 To route external interrupts to the WKPU interrupt controller, the GPIO
14 the following snippet of devicetree source code instructs the GPIO controller
15 to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
24 interrupt controller allows for the allocation of distinct interrupt
26 the fact that each interrupt controller features its own interrupt vector.
[all …]
/Zephyr-Core-3.6.0/drivers/sdhc/
DKconfig.intel13 validated using intel's EMMC host controller.
17 bool "EMMC host controller interrupt mode"
20 EMMC host controller interrupt mode support.
23 bool "EMMC host controller DMA mode"
26 EMMC host controller DMA mode support.
29 bool "EMMC host controller ADMA mode"
32 EMMC host controller ADMA mode support.
35 int "EMMC host controller ADMA Descriptor size"
39 EMMC host controller ADMA Descriptor size.
/Zephyr-Core-3.6.0/subsys/bluetooth/common/
DKconfig16 Controller. This value does not include the HCI ACL header.
17 The Host will segment the data transmitted to the Controller so that
18 packets sent to the Controller will contain data up to this size.
20 Controller.
22 by the Controller and use the smallest value supported by both the
23 Host and the Controller.
26 The Controller will return this value in the HCI LE Read Buffer
28 Layer transmission size then the Controller will perform
41 Controller. This determines the maximum amount of data packets the
42 Host can have queued in the Controller before waiting for the
[all …]
/Zephyr-Core-3.6.0/drivers/i2c/
Di2c_npcx_controller.h17 * @brief Lock the mutex of npcx i2c controller.
19 * @param i2c_dev Pointer to the device structure for i2c controller instance.
24 * @brief Unlock the mutex of npcx i2c controller.
26 * @param i2c_dev Pointer to the device structure for i2c controller instance.
31 * @brief Configure operation of a npcx i2c controller.
33 * @param i2c_dev Pointer to the device structure for i2c controller instance.
35 * for the I2C controller.
44 * @brief Get I2C controller speed.
46 * @param i2c_dev Pointer to the device structure for i2c controller instance.
51 * @retval -EIO Controller is not configured.
[all …]
/Zephyr-Core-3.6.0/drivers/usb/udc/
DKconfig.virtual5 bool "Virtual USB device controller driver"
10 Virtual USB device controller driver.
13 int "Virtual controller driver internal thread stack size"
17 Virtual device controller driver internal thread stack size.
20 int "Virtual controller driver thread priority"
24 Virtual device controller driver thread priority.
DKconfig.skeleton5 bool "Skeleton for an USB device controller driver"
9 Skeleton for an USB device controller driver.
12 int "UDC controller driver internal thread stack size"
16 Skeleton device controller driver internal thread stack size.
19 int "Skeleton controller driver thread priority"
23 Skeleton device controller driver thread priority.
/Zephyr-Core-3.6.0/drivers/memc/
DKconfig.stm325 bool "STM32 Flexible Memory Controller (FMC)"
9 Enable STM32 Flexible Memory Controller.
14 bool "STM32 FMC SDRAM controller"
20 Enable STM32 FMC SDRAM controller.
23 bool "STM32 FMC NOR/PSRAM controller"
30 Enable STM32 FMC NOR/PSRAM controller.
/Zephyr-Core-3.6.0/tests/bluetooth/controller/ctrl_tx_buffer_alloc/
Dtestcase.yaml7 bluetooth.controller.ctrl_tx_buffer_alloc.test_0_per_conn:
10 bluetooth.controller.ctrl_tx_buffer_alloc.test_1_per_conn:
14 bluetooth.controller.ctrl_tx_buffer_alloc.test_2_per_conn:
18 bluetooth.controller.ctrl_tx_buffer_alloc.test_3_per_conn:
22 bluetooth.controller.ctrl_tx_buffer_alloc.test_max_per_conn_alloc:
26 bluetooth.controller.ctrl_tx_buffer_alloc.test_max_common_alloc:
/Zephyr-Core-3.6.0/dts/riscv/
Dvirt.dtsi46 hlic0: interrupt-controller {
50 interrupt-controller;
60 hlic1: interrupt-controller {
64 interrupt-controller;
74 hlic2: interrupt-controller {
78 interrupt-controller;
88 hlic3: interrupt-controller {
92 interrupt-controller;
102 hlic4: interrupt-controller {
106 interrupt-controller;
[all …]
/Zephyr-Core-3.6.0/subsys/bluetooth/controller/
DKconfig1 # Bluetooth Controller configuration options
6 # The following symbols are enabled depending if the controller actually
108 bool "Bluetooth Controller"
110 Enables support for SoC native controller implementations.
127 comment "BLE Controller configuration"
130 bool "Crypto functions in Controller"
135 provided by the controller.
174 Set the number of Rx PDUs to be buffered in the controller. In a 7.5ms
185 controller. Number of required RX buffers would worst-case be
200 in the controller.
[all …]
/Zephyr-Core-3.6.0/doc/hardware/peripherals/
Dsmbus.rst19 Devices on the bus can operate in three roles: as a Controller that
22 Controller, that provides the main interface to the system's CPU.
23 Zephyr has API for the Controller role.
25 SMBus peripheral devices can initiate communication with Controller
29 protocol behaves as a Controller to perform the notification. It writes
33 request attention from the Controller. The Controller needs to read one byte
43 .. _smbus-controller-api:
45 SMBus Controller API
48 Zephyr's SMBus controller API is used when an SMBus device controls the bus,
/Zephyr-Core-3.6.0/dts/riscv/openisa/
Drv32m1.dtsi6 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
17 zephyr,flash-controller = &ftfe;
60 pcc0: clock-controller@4002b000 {
66 pcc1: clock-controller@41027000 {
72 event0: interrupt-controller@e0041000 {
76 interrupt-controller;
80 event1: interrupt-controller@4101f000 {
84 interrupt-controller;
98 intmux0_ch0: interrupt-controller@0 {
102 interrupt-controller;
[all …]
/Zephyr-Core-3.6.0/include/zephyr/drivers/usb/
Dudc.h9 * @brief New USB device controller (UDC) driver API
22 * @brief Maximum packet size of control endpoint supported by the controller.
32 * USB device controller capabilities
37 /** USB high speed capable controller */
39 /** Controller supports USB remote wakeup */
41 /** Controller performs status OUT stage automatically */
43 /** Controller expects device address to be set before status stage */
64 * USB device controller endpoint capabilities
84 * USB device controller endpoint status
100 * USB device controller endpoint configuration
[all …]
/Zephyr-Core-3.6.0/include/zephyr/devicetree/
Dcan.h26 * @brief Get the maximum transceiver bitrate for a CAN controller
29 * controller. If no CAN transceiver is present in the devicetree, the maximum
30 * bitrate will be that of the CAN controller.
41 * compatible = "vnd,can-controller";
46 * compatible = "vnd,can-controller";
60 * @param max maximum bitrate supported by the CAN controller
61 * @return the maximum bitrate supported by the CAN controller/transceiver combination
69 * @brief Get the maximum transceiver bitrate for a DT_DRV_COMPAT CAN controller
71 * @param max maximum bitrate supported by the CAN controller
72 * @return the maximum bitrate supported by the CAN controller/transceiver combination
/Zephyr-Core-3.6.0/samples/bluetooth/hci_uart_async/
DREADME.rst6 Expose a Zephyr Bluetooth Controller over a standard Bluetooth HCI UART interface.
20 By default the controller builds use the following settings:
32 Using the controller with emulators and BlueZ
36 controller and expose it to Linux's BlueZ.
55 Using the controller with QEMU or native_sim
58 In order to use the HCI UART controller with QEMU or :ref:`native_sim <native_sim>` you will need
68 ``/dev/ttyACM0`` string to point to the serial device your controller is
73 interacting with the controller and instead just be aware of it in order
77 Linux kernel identifies the attached controller.
79 Once the controller is attached follow the instructions in the
[all …]
/Zephyr-Core-3.6.0/dts/bindings/memory-controllers/
Dst,stm32-fmc.yaml5 STM32 Flexible Memory Controller (FMC).
11 controller. Each external device is accessed by means of a unique chip select.
14 The flexible memory controller includes three memory controllers:
16 - NOR/PSRAM memory controller
17 - NAND memory controller (some devices also support PC Card)
18 - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
20 Each memory controller is defined below the FMC DeviceTree node and is managed
/Zephyr-Core-3.6.0/tests/drivers/i2c/i2c_target_api/
DREADME.txt12 Zephyr application issues commands to one controller that are responded
13 to by the simulated EEPROM connected through the other controller.
16 controller and target behavior simultaneously. This is not true of all
28 * Issue commands on one bus controller (operating as the bus controller) and
29 verify that the data supplied by the other controller (target) match
34 Transfer of commands from one bus controller to the other is
40 or the controller driver has bugs, the test will fail one or more I2C
/Zephyr-Core-3.6.0/modules/
DKconfig.stm3230 Enable STM32Cube Controller Area Network (CAN) HAL module driver
35 Enable STM32Cube HDMI-CEC controller (CEC) HAL module driver
119 Enable STM32Cube Direct Memory Access controller (DMA) HAL module
125 Enable STM32Cube Chrom-Art Accelerator™ controller (DMA2D) HAL module
131 Enable STM32Cube Extended Direct Memory Access controller (DMA) HAL
157 Enable STM32Cube Extended interrupt and event controller (EXTI) HAL
163 Enable STM32Cube Controller area network with flexible data rate
230 Enable STM32Cube Global TrustZone controller (GTZC) HAL module
246 Enable STM32Cube Host Controller device (HCD) HAL module driver
294 Enable STM32Cube Inter-Processor communication controller (IPCC) HAL
[all …]

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