Searched full:clearing (Results 1 – 25 of 156) sorted by relevance
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/Zephyr-latest/soc/neorv32/ |
D | soc_irq.S | 18 * clearing a pending IRQ. Instead we disable the IRQ in the MIE CSR and 19 * re-enable it (if it was enabled when clearing).
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/Zephyr-latest/dts/bindings/i2c/ |
D | espressif,esp32-i2c.yaml | 25 if the target SoC does not have support in hardware for clearing 32 if the target SoC does not have support in hardware for clearing
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/Zephyr-latest/drivers/serial/ |
D | Kconfig.stm32 | 35 setting/clearing DMAT bit".
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/Zephyr-latest/modules/hal_nordic/nrf_802154/sl_opensource/platform/ |
D | nrf_802154_irq_zephyr.c | 42 /* Zephyr does not provide abstraction layer for clearing pending IRQ */ in nrf_802154_irq_clear_pending()
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/Zephyr-latest/dts/bindings/sensor/ |
D | maxim,max17262.yaml | 42 description: The voltage level for clearing empty detection in mV (default 3880)
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/Zephyr-latest/drivers/hwinfo/ |
D | hwinfo_rw61x.c | 12 /* Because of the ROM clearing the reset register and using scratch register
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D | hwinfo_ambiq.c | 120 * INFO1 space even upon clearing RSTGEN->STAT in z_impl_hwinfo_clear_reset_cause()
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/Zephyr-latest/modules/hal_nordic/nrfs/dvfs/ |
D | ld_dvfs.h | 24 * @brief Function for clearing the zero bias
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/Zephyr-latest/dts/bindings/fpga/ |
D | lattice,ice40-fpga-bitbang.yaml | 37 Register address for clearing a GPIO.
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/Zephyr-latest/drivers/clock_control/ |
D | clock_control_renesas_cpg_mssr.h | 79 /* Software Reset Clearing Register offsets */ 99 /* Software Reset Clearing Register offsets */
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/Zephyr-latest/doc/services/storage/stream/ |
D | stream_flash.rst | 27 The Stream Flash module offers an API for loading, saving and clearing stream
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/Zephyr-latest/lib/utils/ |
D | notify.c | 72 /* Mark completion by clearing the flags field to the in sys_notify_finalize()
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/Zephyr-latest/soc/microchip/mec/common/reg/ |
D | mec_uart.h | 47 #define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */ 48 #define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */
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D | mec_pwm.h | 28 * Enable and start PWM. Clearing this bit resets internal counters.
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/Zephyr-latest/include/zephyr/arch/common/ |
D | ffs.h | 61 * by first clearing all but the lowest set bit. in find_lsb_set()
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/Zephyr-latest/subsys/bluetooth/mesh/ |
D | heartbeat.c | 314 /* Only an explicit address change to unassigned should trigger clearing in bt_mesh_hb_sub_set() 332 /* Clearing the period should stop heartbeat subscription in bt_mesh_hb_sub_set() 333 * without clearing the parameters, so we can still read them. in bt_mesh_hb_sub_set()
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/Zephyr-latest/drivers/timer/ |
D | arcv2_timer0.c | 168 * - reprogramming of LIMIT must be clearing the COUNT 169 * - ISR must be clearing the 'overflow_cycles' counter. 320 * between cycle_count and clearing 0, few cycles are possible in sys_clock_set_timeout()
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/Zephyr-latest/boards/renesas/rcar_salvator_x/support/ |
D | openocd.cfg | 34 # Software Reset Clearing Register 2 Bit(22) Arm Realtime core
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/Zephyr-latest/arch/arm/core/cortex_m/ |
D | isr_wrapper.c | 44 * non-tickless idle, this ensures that the clearing of the kernel idle in _isr_wrapper()
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/Zephyr-latest/drivers/usb_c/tcpc/ |
D | ucpd_stm32_priv.h | 43 * @brief UCPD alert mask used for clearing alerts 62 * @brief UCPD alert mask used for clearing alerts
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/Zephyr-latest/doc/connectivity/bluetooth/api/mesh/ |
D | proxy.rst | 50 :ref:`bluetooth_mesh_srpl_srv`, provide the functionality of saving and clearing SRPL entries. A
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/Zephyr-latest/arch/x86/core/ |
D | cache.c | 35 /* Enable write-back caching by clearing the NW and CD bits */ in arch_dcache_enable()
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/Zephyr-latest/drivers/watchdog/ |
D | wdt_dw.c | 124 * Once watchdog is enabled by setting WDT_EN bit watchdog cannot be disabled by clearing 221 * Clearing interrupt here will not assert system reset, so interrupt
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/Zephyr-latest/drivers/dai/intel/dmic/ |
D | dmic_nhlt.h | 57 * by the driver just by clearing CIC_CONTROL.SOFT_RESET bit.
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/Zephyr-latest/dts/bindings/memory-controllers/ |
D | renesas,ra-sdram.yaml | 129 - TREFW: Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
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