Searched +full:axistream +full:- +full:connected (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-latest/dts/bindings/dma/ |
| D | xilinx,axi-dma-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: dma-controller.yaml
21 interrupt-parent:
23 description: Interrupt controller that the DMA is connected to
26 type: phandle-array
28 clock-frequency:
36 - 32
37 - 64
39 axistream-connected:
42 Handle to connected node, e.g., AXI Ethernet controller.
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| /Zephyr-latest/drivers/dma/ |
| D | dma_xilinx_axi_dma.c | 7 * SPDX-License-Identifier: Apache-2.0
40 /* internal DMA error, e.g., 0-length transfer */
59 /* interrupt timeout - trigger interrupt after X cycles when no transfer. Unit is 125 * */
62 /* irqthreshold - this can be used to generate interrupts after X completed packets */
84 /* run-stop */
118 /* RS (run-stop) in DMACR is 0 and operations completed; writing tail does nothing */
147 /* in-memory descriptor, read by the DMA, that instructs it how many bits to transfer from which */
150 /* next descriptor[31:6], bits 5-0 reserved */
166 /* application-specific fields used, e.g., to enable checksum offloading */
216 /* this should always be 2 - one for TX, one for RX */
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