Home
last modified time | relevance | path

Searched +full:apb7 +full:- +full:prescaler (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dhse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(32)>;
19 ahb-prescaler = <1>;
20 ahb5-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hse-div2;
19 clock-frequency = <DT_FREQ_M(16)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16_ahb5_div.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 ahb5-div;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb7-prescaler = <1>;
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb7-prescaler = <1>;
Dpll_hse_100.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 clock-frequency = <DT_FREQ_M(100)>;
29 ahb-prescaler = <1>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
Dpll_hse_100_ahb_50.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>;
18 div-m = <8>;
19 mul-n = <100>;
20 div-q = <2>;
21 div-r = <4>;
28 ahb-prescaler = <2>;
29 clock-frequency = <DT_FREQ_M(50)>;
30 ahb5-prescaler = <4>;
31 apb1-prescaler = <1>;
[all …]
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-div2;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-q;
25 /delete-property/ div-r;
26 /delete-property/ clocks;
31 /delete-property/ clocks;
32 /delete-property/ clock-frequency;
33 /delete-property/ ahb-prescaler;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 matching prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
25 apb7-presacler = <7>;
55 compatible: "st,stm32wba-rcc"
[all …]
/Zephyr-latest/boards/st/nucleo_wba52cg/
Dnucleo_wba52cg.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wba/stm32wba52cgux-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32WBA52CG-NUCLEO board";
15 compatible = "st,stm32wba52cg-nucleo";
17 #address-cells = <1>;
18 #size-cells = <1>;
22 zephyr,shell-uart = &usart1;
25 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-latest/boards/st/nucleo_wba55cg/
Dnucleo_wba55cg.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wba/stm32wba55cgux-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "STMicroelectronics STM32WBA55CG-NUCLEO board";
15 compatible = "st,stm32wba55cg-nucleo";
17 #address-cells = <1>;
18 #size-cells = <1>;
21 zephyr,bt-c2h-uart = &usart1;
22 zephyr,uart-pipe = &usart1;
[all …]
/Zephyr-latest/dts/arm/st/wba/
Dstm32wba.dtsi2 * Copyright (c) 2023-2024 STMicroelectronics
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
10 #include <zephyr/dt-bindings/clock/stm32wba_clock.h>
11 #include <zephyr/dt-bindings/reset/stm32wba_reset.h>
12 #include <zephyr/dt-bindings/adc/stm32u5_adc.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
[all …]