| /Zephyr-Core-3.5.0/dts/bindings/mtd/ |
| D | jedec,spi-nor-common.yaml | 3 # SPDX-License-Identifier: Apache-2.0
5 # Common properties used by nodes describing M25P80-compatible SPI NOR
8 # This extends JESD216-defined features with additional functionality
9 # that may be specific to the vendor of a M25P80-compatible device and
17 requires-ulbpr:
23 protection register that initializes to write-protected. Use this
27 has-dpd:
33 Power-Down mode that is entered by command 0xB9 to reduce power
35 implies that the RDPD (0xAB) Release from Deep Power Down command
37 Electronic Signature; see t-enter-dpd).
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| D | atmel,at45.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [spi-device.yaml]
11 jedec-id:
12 type: uint8-array
21 sector-size:
26 sector-0a-pages:
38 block-size:
43 page-size:
48 no-chip-erase:
53 no-sector-erase:
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| /Zephyr-Core-3.5.0/samples/drivers/i2s/echo/src/ |
| D | codec.c | 4 * SPDX-License-Identifier: Apache-2.0
29 * Power Down Control: in init_wm8731_i2c()
31 * [6] CLKOUTPD = 1 (Enable Power Down) in init_wm8731_i2c()
32 * [5] OSCPDD = 0 (Disable Power Down) in init_wm8731_i2c()
33 * [4] OUTPD = 1 (Enable Power Down) in init_wm8731_i2c()
34 * [3] DACPD = 0 (Disable Power Down) in init_wm8731_i2c()
35 * [2] ADCPD = 0 (Disable Power Down) in init_wm8731_i2c()
36 * [1] MICPD = 1 (Enable Power Down) in init_wm8731_i2c()
37 * [0] LINEINPD = 0 (Disable Power Down) in init_wm8731_i2c()
44 * [4:0] LINVOL = 0x07 (-24 dB) in init_wm8731_i2c()
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | st,lis2ds12-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 irq-gpios:
8 type: phandle-array
20 Range in g. Default is power-up configuration.
23 - 16 # 16g (0.488 mg/LSB)
24 - 8 # 8g (0.244 mg/LSB)
25 - 4 # 4g (0.122 mg/LSB)
26 - 2 # 2g (0.061 mg/LSB)
28 power-mode:
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| D | st,ism330dhcx-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 drdy-gpios:
8 type: phandle-array
16 int-pin:
29 configuration at power-up.
31 - 1
32 - 2
34 accel-odr:
39 Default is power-up configuration.
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| D | st,lsm6dso-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 irq-gpios:
8 type: phandle-array
16 int-pin:
20 - 1 # drdy is generated from INT1
21 - 2 # drdy is generated from INT2
28 configuration at power-up.
30 accel-pm:
34 Specify the accelerometer power mode.
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| D | st,lsm6dso16is-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 irq-gpios:
8 type: phandle-array
16 drdy-pin:
20 - 1 # drdy is generated from INT1
21 - 2 # drdy is generated from INT2
28 configuration at power-up.
30 accel-range:
34 Range in g. Default is power-up configuration.
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| D | ti,ina219.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Texas Instruments Bidirectional Current/Power Sensor
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
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| D | st,lps22hh-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 drdy-gpios:
8 type: phandle-array
21 The default is the power-on reset value.
23 - 0 # Power-Down
24 - 1 # 1Hz
25 - 2 # 10Hz
26 - 3 # 25Hz
27 - 4 # 50Hz
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ |
| D | adsp_power.h | 3 * SPDX-License-Identifier: Apache-2.0
17 /* Power Control register - controls the power domain operations. */
34 /* Power Status register - reports the power domain status. */
50 * @brief Power up a specific CPU.
52 * This sets the "not power gating" bit in the power control
53 * register to disable power gating to CPU, thus powering up
60 ACE_PWRCTL->wpdsphpxpg |= BIT(cpu_num); in soc_cpu_power_up()
64 * @brief Power down a specific CPU.
66 * This clears the "not power gating" bit in the power control
67 * register to enable power gating to CPU, thus powering down
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | pm_cpu_ops.h | 4 * SPDX-License-Identifier: Apache-2.0
12 * @brief Public API for CPU Power Management
27 * @defgroup power_management_cpu_api CPU Power Management
33 * @brief Power down the calling core
35 * This call is intended for use in hotplug. A core that is powered down by
39 * @retval -ENOTSUP If the operation is not supported
44 * @brief Power up a core
46 * This call is used to power up cores that either have not yet been booted
47 * into the calling supervisory software or have been previously powered down
50 * @param cpuid CPU id to power on
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/ |
| D | adsp_power.h | 3 * SPDX-License-Identifier: Apache-2.0
29 /* Power control */
50 * @brief Power up a specific CPU.
52 * This sets the "not power gating" bit in the power control
53 * register to disable power gating to CPU, thus powering up
60 ACE_PWRCTL->wpdsphpxpg |= BIT(cpu_num); in soc_cpu_power_up()
64 * @brief Power down a specific CPU.
66 * This clears the "not power gating" bit in the power control
67 * register to enable power gating to CPU, thus powering down
70 * @param cpu_num CPU to be powered down.
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| /Zephyr-Core-3.5.0/doc/hardware/peripherals/ |
| D | rtc.rst | 3 Real-Time Clock (RTC)
9 .. list-table:: **Glossary**
11 :header-rows: 1
13 * - Word
14 - Definition
15 * - Real-time clock
16 - Low power device tracking time using broken-down time
17 * - Real-time counter
18 - Low power counter which can be used to track time
19 * - RTC
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| /Zephyr-Core-3.5.0/samples/boards/mimxrt595_evk_cm33/system_off/ |
| D | sample.yaml | 4 # SPDX-License-Identifier: Apache-2.0
7 name: Deep Power Down State Sample for mimxrt595_evk
9 tags: power
|
| /Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
11 prompt "ESP32-C3 SOC Selection"
72 - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
73 - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
78 int "Max WiFi TX power (dBm)"
82 Set maximum transmit power for WiFi radio. Actual transmit power for high
90 bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
94 If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered
95 down when PHY is disabled. Enabling this setting reduces power consumption
96 by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
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| /Zephyr-Core-3.5.0/drivers/flash/ |
| D | Kconfig.nor | 1 # Copyright (c) 2018 Savoir-Faire Linux.
2 # SPDX-License-Identifier: Apache-2.0
24 jedec-id properties in the devicetree jedec,spi-nor node.
30 sfdp-bfp property in devicetree. The size and jedec-id properties are
38 for all supported JESD216-compatible devices.
62 size (65536). Other options include the 32K-byte erase size
63 (32768), the sector size (4096), or any non-zero multiple of the
67 bool "Use Deep Power-Down mode when flash is not being accessed."
69 Where supported deep power-down mode can reduce current draw
73 Select this option for applications where device power
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| /Zephyr-Core-3.5.0/soc/arm/arm/beetle/ |
| D | soc_registers.h | 4 * SPDX-License-Identifier: Apache-2.0
85 /* Offset: 0x0d0 (r/w) AHB power down sleep wakeup source set */
87 /* Offset: 0x0d4 (r/w) AHB power down sleep wakeup source clear */
89 /* Offset: 0x0d8 (r/w) APB power down sleep wakeup source set */
91 /* Offset: 0x0dc (r/w) APB power down sleep wakeup source clear */
98 /* Offset: 0x0f0 (r/w) sram power control override */
100 /* Offset: 0x0f4 (r/w) embedded flash power control override */
|
| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/ |
| D | power.c | 4 * SPDX-License-Identifier: Apache-2.0
22 #include <cavs-idc.h>
63 * @brief Power down procedure.
65 * Locks its code in L1 cache and shuts down memories.
69 * @param hpsram_pg_mask pointer to memory segments power gating mask
100 imr_layout->imr_state.header = hdr; in pm_state_set()
103 /* turn off all HPSRAM banks - get a full bitmap */ in pm_state_set()
107 /* do power down - this function won't return */ in pm_state_set()
114 __ASSERT(false, "invalid argument - unsupported power state"); in pm_state_set()
118 /* Handle SOC specific activity after Low Power Mode Exit */
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | pincfg-node.yaml | 2 # SPDX-License-Identifier: Apache-2.0
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
31 bias-pull-up:
33 description: enable pull-up resistor
35 bias-pull-down:
37 description: enable pull-down resistor
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| D | nordic,nrf-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
20 /* You can put this in places like a board-pinctrl.dtsi file in
35 /* both P0.3 and P0.4 are configured with pull-up */
36 bias-pull-up;
43 state. You would specify the low-power configuration for the same device
52 include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h header file.
55 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
58 - bias-disable: Disable pull-up/down (default behavior, not required).
59 - bias-pull-up: Enable pull-up resistor.
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| D | microchip,xec-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
28 - bias-pull-up: Enable pull-up resistor.
29 - drive-push-pull: Output driver is push-pull (default, not required).
30 - drive-open-drain: Output driver is open-drain.
31 - output-high: Set output state high when pin configured.
32 - output-low: Set output state low when pin configured.
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| /Zephyr-Core-3.5.0/dts/bindings/sdhc/ |
| D | zephyr,sdhc-spi-slot.yaml | 3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
12 Time in ms for SPI SDHC to delay when toggling power to the SD card. This
13 delay gives the card time to power up or down fully. It can be increased
16 spi-clock-mode-cpol:
22 spi-clock-mode-cpha:
26 on the clock's polarity. When mode-cpol is set and this option as well,
30 pwr-gpios:
31 type: phandle-array
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
21 DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
22 DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc
71 int "Bytes to reserve at start of HP-SRAM"
74 Bytes to reserve at the start of HP-SRAM. Zephyr will not
90 Need to power cache SRAM banks on.
103 Switch off HP SRAM during power down.
109 bool "Saves FW context into IMR before core is shut down"
114 when Host power up DSP again.
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| /Zephyr-Core-3.5.0/doc/services/pm/ |
| D | power_domain.rst | 1 .. _pm-power-domain:
3 Power Domain
9 The Zephyr power domain abstraction is designed to support groupings of devices
10 powered by a common source to be notified of power source state changes in a
12 that device B is on the same power domain and should also be configured into a
13 low power state.
15 Power domains are optional on Zephyr, to enable this feature the
18 When a power domain turns itself on or off, it is the responsibility of the
19 power domain to notify all devices using it through their power management
25 .. _pm-domain-work-flow:
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| /Zephyr-Core-3.5.0/boards/arm/gd32l233r_eval/doc/ |
| D | index.rst | 3 GigaDevice GD32L233R-EVA
9 The GD32L233R-EVAL board is a hardware platform that enables design and debug
10 of the GigaDevice GD32L233 Cortex-M23 Low Power MCU.
12 The GD32RCT6 features a single-core ARM Cortex-M4F MCU which can run up
13 to 64-MHz with flash accesses zero wait states, 256kB of Flash, 32kB of
23 - GD32L233RCT6 MCU
24 - AT24C02C 2Kb EEPROM
25 - 4 x User LEDs
26 - 2 x User Push buttons
27 - 1 x USART (Mini-USB)
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