1# Intel CAVS SoC family configuration options
2#
3# Copyright (c) 2020 Intel Corporation
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_FAMILY_INTEL_ADSP
7	select WINSTREAM
8	select ARCH_SUPPORTS_COREDUMP
9	select CPU_HAS_DCACHE
10	bool
11
12if SOC_FAMILY_INTEL_ADSP
13
14config SOC_FAMILY
15	string
16	default "intel_adsp"
17
18# Select SoC Part No. and configuration options
19source "soc/xtensa/intel_adsp/*/Kconfig.soc"
20
21DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc
22DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc
23
24config INTEL_ADSP_IPC
25	bool "Driver for the host IPC interrupt delivery"
26	default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF
27	default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF
28	help
29	  Driver for the host IPC interrupt delivery mechanism.
30	  Currently SOF has its own driver for this hardware.
31
32config MEMORY_WIN_0_SIZE
33	int "Size of memory window 0"
34	default 8192
35	help
36	  Size of memory window 0.
37
38	  This window is used for firmware status & outbox/uplink mbox.
39
40config MEMORY_WIN_1_SIZE
41	int "Size of memory window 1"
42	default 8192
43	help
44	  Size of memory window 1.
45
46	  This window is used for inbox/downlink mbox.
47
48config MEMORY_WIN_2_SIZE
49	int "Size of memory window 2"
50	default 8192
51	help
52	  Size of memory window 2.
53
54	  This window is used for debug.
55
56config MEMORY_WIN_3_SIZE
57	int "Size of memory window 3"
58	default 8192
59	help
60	  Size of memory window 3.
61
62	  This window is used for trace.
63
64config ADSP_CLOCK
65	bool
66	help
67	  Driver for the CAVS clocks. Allow type of clock (and
68	  thus frequency) to be chosen.
69
70config HP_SRAM_RESERVE
71	int "Bytes to reserve at start of HP-SRAM"
72	default 65536
73	help
74	  Bytes to reserve at the start of HP-SRAM.  Zephyr will not
75	  place any symbols here, though the host windows have
76	  addresses here.  The SOF application also makes direct use
77	  of this region, so be very careful changing this value.
78
79config ADSP_TRACE_SIMCALL
80	bool "Emit SIMCALL output in addition to window tracing"
81	help
82	  When true, the trace_out layer will also use a SIMCALL
83	  instruction to emit the passed data to the standard output
84	  of an enclosing simulator process.  All window contents will
85	  remain identical.
86
87config ADSP_NEED_POWER_ON_CACHE
88	bool
89	help
90	  Need to power cache SRAM banks on.
91
92config ADSP_INIT_HPSRAM
93	bool
94	default y
95	help
96	  Need to init HP SRAM.
97
98config ADSP_POWER_DOWN_HPSRAM
99	bool
100	default n if ZTEST
101	default y
102	help
103	 Switch off HP SRAM during power down.
104
105config ADSP_DISABLE_L2CACHE_AT_BOOT
106	bool
107
108config ADSP_IMR_CONTEXT_SAVE
109	bool "Saves FW context into IMR before core is shut down"
110	default n
111	help
112	  When true, FW will store its entire context into IMR before
113	  entering D3 state. Later this context can be used to FW restore
114	  when Host power up DSP again.
115
116endif # SOC_FAMILY_INTEL_ADSP
117