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/hal_gigadevice-latest/scripts/tests/gd32pinctrl/data/
Dgd32f999xx.yml53 PA5:
65 pins: [PA3, null, PA4, PA5]
67 pins: [PA4, null, PA5, PA2]
69 pins: [PA5, null, PA2, PA3]
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_cmp.c60 \arg CMP_DAC_OUT: CMP inverting input DAC_OUT(PA4��PA5)
67 \arg CMP_IM_PA5: CMP inverting input PA5
76 \arg CMP_IP_PA5: CMP plus input PA5
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_cmp.h83 CMP_IM_PA5 = 46, /*!< PA5 */
95 CMP_IP_PA5, /*!< PA5 */
154 …5 CS_CMPMSEL(46) /*!< CMP inverting external input PA5 */
165 … CS_CMPPSEL_PA5 CS_CMPPSEL(6) /*!< CMP plus input PA5 */
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_cmp.h86 CMP_PA5, /*!< PA5 input */
126 …MP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/
161 …P1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_cmp.h107 CMP_PA5, /*!< PA5 input */
138 … CS_CMPMSEL(5) /*!< CMP inverting input PA5 */
Dgd32e50x_gpio.h352 #define AFIO_PCFA_PA5_AFCFG BIT(10) /*!< PA5 AF function configuration bit…
601 …PCFA_PA5_AFCFG /*!< configure PA5 alternate function …
/hal_gigadevice-latest/pinconfigs/
Dgd32vf103xx.yml399 PA5:
651 pins: [PA5, PB3]
Dgd32e103xx.yml466 PA5:
710 pins: [PA5, PB3]
Dgd32f403xx.yml500 PA5:
850 pins: [PA5, PB3]
Dgd32f350xx.yml141 PA5:
Dgd32e507xx.yml717 PA5:
1087 pins: [PA5, PB3]
Dgd32a503xx.yml74 PA5:
Dgd32l233xx.yml255 PA5:
Dgd32f405xx.yml87 PA5:
Dgd32f407xx.yml95 PA5:
Dgd32f450xx.yml96 PA5:
Dgd32f470xx.yml96 PA5:
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_cmp.c66 \arg CMP_PA5: PA5 input
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_cmp.c63 \arg CMP_PA5: PA5 input
Dgd32e50x_gpio.c420 \arg AFIO_PA5_USBHS_CFG: configure PA5 alternate function to USBHS