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/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-lfclk.yaml5 nRF LFCLK (Low Frequency CLocK)
7 The LFCLK can use the following clocks as clock sources:
10 LFCLK SYNTH mode is selected and the LFXO clock is not
15 LFCLK SYNTH mode is selected and the LFXO clock is
21 lfclk {
28 compatible: "nordic,nrf-lfclk"
/Zephyr-latest/samples/boards/nordic/clock_control/
Dsample.yaml17 sample.boards.nrf.clock_control.lfclk:
18 filter: dt_nodelabel_enabled("lfclk")
20 - CONF_FILE="configs/lfclk.conf"
21 - DTC_OVERLAY_FILE="configs/lfclk.overlay"
/Zephyr-latest/drivers/clock_control/
DKconfig.npcx16 bool "Generate LFCLK by on-chip Crystal Oscillator"
18 When this option is enabled, the internal 32.768 KHz clock (LFCLK)
Dnrf_clock_calibration.h16 * @brief Initialize LFCLK RC calibration.
Dclock_control_npcm.c108 #define LFCLK 32768 macro
283 *rate = LFCLK; in npcm_clock_control_get_subsys_rate()
Dclock_control_nrf2_lfclk.c58 STRUCT_CLOCK_CONFIG(lfclk, ARRAY_SIZE(clock_options)) clk_cfg;
Dclock_control_nrf.c493 * It can be determined by checking current LFCLK source. If it in lfclk_spinwait()
714 IF_ENABLED(CONFIG_LOG, (.name = "lfclk",))
Dclock_control_npcx.c103 *rate = LFCLK; in npcx_clock_control_get_subsys_rate()
/Zephyr-latest/samples/boards/nordic/clock_control/configs/
Dlfclk.overlay9 sample-clock = &lfclk;
/Zephyr-latest/samples/boards/nordic/clock_skew/
DREADME.rst10 skew between HFCLK (used for the CPU) and LFCLK (used for system time).
12 LFCLK domain to durations in the HFCLK domain.
44 Power-up clocks: LFCLK[ON]: Running LFXO ; HFCLK[OFF]: Running HFINT
46 Timer-running clocks: LFCLK[ON]: Running LFXO ; HFCLK[OFF]: Running HFINT
/Zephyr-latest/drivers/watchdog/
Dwdt_npcx.c19 * LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
45 /* Watchdog operating frequency is fixed to LFCLK (32.768) kHz */
46 #define NPCX_WDT_CLK LFCLK
363 * - T0 Timer freq is LFCLK/32 Hz in wdt_npcx_init()
364 * - Watchdog freq is T0CLK/32 Hz (ie. LFCLK/1024 Hz) in wdt_npcx_init()
/Zephyr-latest/dts/common/nordic/
Dnrf54h20.dtsi195 lfclk: lfclk { label
196 compatible = "nordic,nrf-lfclk";
298 clocks = <&lfclk>;
306 clocks = <&lfclk>;
343 clocks = <&lfclk>;
351 clocks = <&lfclk>;
424 clocks = <&lfclk>;
740 clocks = <&lfclk>;
752 clocks = <&lfclk>;
761 clocks = <&lfclk>;
[all …]
/Zephyr-latest/drivers/sensor/nuvoton/nuvoton_tach_npcx/
Dtach_nuvoton_npcx.c25 * LFCLK--------------------->| | +-----------+ TB Pin
112 SET_FIELD(inst->TCKC, NPCX_TCKC_C1CSEL_FIELD, data->input_clk == LFCLK in tach_npcx_start_port_a()
136 SET_FIELD(inst->TCKC, NPCX_TCKC_C2CSEL_FIELD, data->input_clk == LFCLK in tach_npcx_start_port_b()
229 } else if (data->input_clk == LFCLK) { in tach_npcx_configure()
/Zephyr-latest/drivers/pwm/
Dpwm_npcx.c68 /* Select APB CLK/LFCLK clock sources to PWM module by default */ in pwm_npcx_configure()
72 /* Select clock source to LFCLK by flag, otherwise APB clock source */ in pwm_npcx_configure()
Dpwm_nrf_sw.c223 * task event is generated always one LFCLK cycle after period in pwm_nrf_sw_set_cycles()
/Zephyr-latest/drivers/timer/
Dnpcx_itim_timer.c27 * by LFCLK which frequency is 32KHz and still activated when ec entered
51 #define EVT_CYCLES_PER_SEC LFCLK /* 32768 Hz */
117 * asynchronization between core and itim32's source clock (LFCLK). in npcx_itim_evt_enable()
/Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/
Dmain.c150 .clk_dev = DEVICE_DT_GET(DT_NODELABEL(lfclk)),
273 TC_PRINT("LFCLK test\n"); in ZTEST()
/Zephyr-latest/boards/nuvoton/npcx7m6fb_evb/
Dnpcx7m6fb_evb.dts89 sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
/Zephyr-latest/boards/nuvoton/npcx9m6f_evb/
Dnpcx9m6f_evb.dts101 sample-clk = <NPCX_TACH_FREQ_LFCLK>; /* Use LFCLK as sampling clock */
/Zephyr-latest/soc/nuvoton/npcx/common/
Dpower.c18 * | Power State | LFCLK | HFCLK | APB/AHB | Core | RAM/Regs | VCC | VSBY |
27 * LFCLK - Low-Frequency Clock. Its frequency is fixed to 32kHz.
Dsoc_clock.h74 #define LFCLK 32768 macro
/Zephyr-latest/tests/drivers/clock_control/nrf_clock_calibration/src/
Dtest_nrf_clock_calibration.c15 #error "LFCLK must use RC source"
/Zephyr-latest/samples/boards/nordic/clock_skew/src/
Dmain.c106 printk("%s: LFCLK[%s]: %s %s ; ", tag, clkstat_s[clkstat], in show_clocks()
/Zephyr-latest/doc/releases/
Drelease-notes-2.5.rst1427 * :github:`29762` - nRF53 Network core cannot start LFClk when using empty_app_core