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/Zephyr-Core-3.5.0/samples/drivers/fpga/fpga_controller/src/
Dmain.c20 IO_MUX->PAD_21_CTRL = (PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL | in main()
23 IO_MUX->PAD_22_CTRL = (PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL | in main()
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_eos_s3.c147 uint32_t *io_mux = (uint32_t *)IO_MUX; in gpio_eos_s3_configure() local
192 io_mux += gpio_cfg.xPadConf->ucPin; in gpio_eos_s3_configure()
193 *io_mux &= ~PAD_OEN_DISABLE; in gpio_eos_s3_configure()
194 *io_mux |= PAD_REN_ENABLE; in gpio_eos_s3_configure()
/Zephyr-Core-3.5.0/dts/bindings/spi/
Despressif,esp32-spi.yaml61 Some pins are allowed to bypass the GPIO Matrix and use the IO_MUX
/Zephyr-Core-3.5.0/drivers/fpga/
Dfpga_eos_s3.c129 IO_MUX->PAD_19_CTRL = PAD_ENABLE; in eos_s3_fpga_init()
/Zephyr-Core-3.5.0/boards/xtensa/olimex_esp32_evb/doc/
Dindex.rst69 | IO_MUX | on-chip | pinctrl |