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/Zephyr-latest/dts/bindings/clock/
Dst,stm32g0-hsi-clock.yaml5 STM32 HSI Clock node description for STM32G0 devices
6 On STM32G0, HSI is a 16MHz fixed clock.
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
10 SYSCLK = HSI16 / HSI DIV
21 compatible: "st,stm32g0-hsi-clock"
26 hsi-div:
30 HSI clock divider. Configures the output HSI clock frequency (HSISYS),
31 It does not apply to HSI clk selected as peripheral source clock
32 (eg: RNG clk driven by HSI)
Dst,stm32c0-hsi-clock.yaml5 STM32 HSI Clock node description for STM32C0 devices
6 On STM32C0, HSI is a 48MHz fixed clock.
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
10 SYSCLK = HSI48 / HSI DIV
21 compatible: "st,stm32c0-hsi-clock"
26 hsi-div:
30 HSI clock divider. Configures the output HSI clock frequency (HSISYS).
Dst,stm32h7-hsi-clock.yaml4 description: STM32 HSI Clock
6 compatible: "st,stm32h7-hsi-clock"
11 hsi-div:
15 HSI clock divider. Configures the output HSI clock frequency
Dwch,ch32v00x-hsi-clock.yaml4 description: WCH CH32V00x HSI Clock
6 compatible: "wch,ch32v00x-hsi-clock"
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dhsi_g0_16.overlay12 &clk_hsi { /* HSI RC: 16MHz, hsi_clk = 16MHz */
14 hsi-div = <1>;
Dhsi_16.overlay12 &clk_hsi { /* HSI RC: 16MHz, hsi_clk = 16MHz */
Dhsi_8.overlay12 &clk_hsi { /* HSI RC: 8MHz, hsi_clk = 8MHz */
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dhsi_64.overlay13 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
Dpll_hsi_96.overlay13 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
Dpll_hsi_fracn_550.overlay13 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_per_ck_hsi.overlay14 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
/Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/
Dnucleo_h563zi.overlay8 /* Set domain clock to HSI to allow wakeup from Stop mode */
27 /* Make sure HSI is enabled */
Db_u585i_iot02a.overlay16 /* Set domain clock to HSI to allow wakeup from Stop mode */
35 /* Make sure HSI is enabled */
Dnucleo_wb55rg.overlay17 /* Set domain clock to HSI to allow wakeup from Stop mode */
36 /* Make sure HSI is enabled */
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dpll_hsi_240.overlay14 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
/Zephyr-latest/soc/st/stm32/stm32wbx/
Dpower.c24 * @brief Switch the system clock on HSI
50 /* The switch on HSI before entering Stop Mode is required */ in lpm_hsem_lock()
54 /* The switch on HSI before entering Stop Mode is required */ in lpm_hsem_lock()
66 /* ensure HSI is the wake-up system clock */ in pm_state_set()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c344 * Unconditionally switch the system clock source to HSI.
349 /* Enable HSI if not enabled */ in stm32_clock_switch_to_hsi()
351 /* Enable HSI */ in stm32_clock_switch_to_hsi()
354 /* Wait for HSI ready */ in stm32_clock_switch_to_hsi()
358 /* Set HSI as SYSCLCK source */ in stm32_clock_switch_to_hsi()
363 /* Erratum 2.2.4: Spurious deactivation of HSE when HSI is selected as in stm32_clock_switch_to_hsi()
365 * Re-enable HSE clock if required after switch source to HSI in stm32_clock_switch_to_hsi()
390 /* Can be HSE, HSI */ in set_up_plls()
459 /* Enable HSI if not enabled */ in set_up_fixed_clock_sources()
461 /* Enable HSI */ in set_up_fixed_clock_sources()
[all …]
Dclock_stm32_ll_h5.c410 /* Enable HSI if not enabled */ in clock_switch_to_hsi()
412 /* Enable HSI */ in clock_switch_to_hsi()
415 /* Wait for HSI ready */ in clock_switch_to_hsi()
419 /* Set HSI as SYSCLCK source */ in clock_switch_to_hsi()
439 * Switch to HSI and disable the PLL before configuration. in set_up_plls()
440 * (Switching to HSI makes sure we have a SYSCLK source in in set_up_plls()
450 /* Configure PLL source : Can be HSE, HSI, MSIS */ in set_up_plls()
637 /* HSI calibration */ in set_up_fixed_clock_sources()
640 /* Enable HSI if not enabled */ in set_up_fixed_clock_sources()
642 /* Enable HSI */ in set_up_fixed_clock_sources()
[all …]
Dclock_stm32_ll_common.c535 * Unconditionally switch the system clock source to HSI.
540 /* Enable HSI if not enabled */ in stm32_clock_switch_to_hsi()
542 /* Enable HSI */ in stm32_clock_switch_to_hsi()
545 /* Wait for HSI ready */ in stm32_clock_switch_to_hsi()
549 /* Set HSI as SYSCLCK source */ in stm32_clock_switch_to_hsi()
562 * Switch to HSI and disable the PLL before configuration. in set_up_plls()
563 * (Switching to HSI makes sure we have a SYSCLK source in in set_up_plls()
582 * Disable PLL2 after switching to HSI for SysClk in set_up_plls()
663 /* Enable HSI if not enabled */ in set_up_fixed_clock_sources()
665 /* Enable HSI */ in set_up_fixed_clock_sources()
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/
Dtest_stm32_clock_configuration.c39 "Expected sysclk src: HSI. Actual sysclk src: %d", in ZTEST()
61 "Expected PLL src: HSI. Actual PLL src: %d", in ZTEST()
/Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/
DREADME.rst26 that can be requested dynamically by device on activity detection (HSI on STM32WB).
32 Note: Using HSI clock is a specific
83 - Ensure no other oscillators are enabled (disable HSI, ...)
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/
Dtest_stm32_clock_configuration.c48 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
76 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
80 "Expected PLL src: HSI (%d). Actual PLL src: %d", in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/
Dtest_stm32_clock_configuration.c39 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
66 "Expected PLL src: HSI. Actual PLL src: %d", in ZTEST()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/
Dtest_stm32_clock_configuration.c39 "Expected sysclk src: HSI (0x%x). Actual: 0x%x", in ZTEST()
66 "Expected PLL src: HSI. Actual PLL src: %d", in ZTEST()
/Zephyr-latest/samples/subsys/usb_c/sink/boards/
Dweact_stm32g431_core.overlay23 /* The HSI is used by ucpd1 */

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