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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml198 programmable divider controlled by the FIUDIV field in HFCBCD1 register.
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h69 * - CORE_CLK > MAX_OFMCLK/2, FIUDIV should be 1, else 0.