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/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
55 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
/Zephyr-latest/dts/bindings/clock/
Dst,stm32wba-pll-clock.yaml64 PLLx DIVR division factor
Dst,stm32u5-pll-clock.yaml70 PLLx DIVR division factor