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/Zephyr-latest/arch/arm/core/cortex_m/
DKconfig1 # ARM Cortex-M platform configuration options
3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
10 # if one select a different ARM Cortex Family (Cortex-A or Cortex-R)
17 This option signifies the use of a Cortex-M0 CPU
24 This option signifies the use of a Cortex-M0+ CPU
31 This option signifies the use of a Cortex-M1 CPU
38 This option signifies the use of a Cortex-M3 CPU
46 This option signifies the use of a Cortex-M4 CPU
54 This option signifies the use of a Cortex-M23 CPU
[all …]
/Zephyr-latest/samples/subsys/llext/modules/
Dsample.yaml4 - qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
5 - qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA)
6 - qemu_cortex_a53 # ARM Cortex-A53 (ARMv8-A ISA)
7 - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA)
8 - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA)
9 - qemu_xtensa/dc233c
11 - qemu_xtensa/dc233c
12 - mps2/an385
13 - qemu_cortex_a53
23 - CONFIG_HELLO_WORLD_MODE=m
[all …]
/Zephyr-latest/arch/arm/include/cortex_m/
Dstack.h2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Stack helpers for Cortex-M CPUs
36 * On Cortex-M, the interrupt stack is registered in the MSP (main stack
51 #error "Built-in MSP limit checks not supported by HW" in z_arm_interrupt_stack_setup()
56 /* Enforce double-word stack alignment on exception entry in z_arm_interrupt_stack_setup()
57 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest in z_arm_interrupt_stack_setup()
58 * of ARM Cortex-M processors this setting is enforced by in z_arm_interrupt_stack_setup()
62 SCB->CCR |= SCB_CCR_STKALIGN_Msk; in z_arm_interrupt_stack_setup()
/Zephyr-latest/doc/services/portability/
Dcmsis_rtos_v1.rst6 Cortex-M Software Interface Standard (CMSIS) RTOS is a vendor-independent
7 hardware abstraction layer for the ARM Cortex-M processor series and defines
8 generic tool interfaces. Though it was originally defined for ARM Cortex-M
/Zephyr-latest/drivers/timer/
DKconfig.cortex_m_systick1 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
6 DT_CHOSEN_IDLE_TIMER := zephyr,cortex-m-idle-timer
9 bool "Cortex-M SYSTICK timer"
20 This module implements a kernel device driver for the Cortex-M processor
27 This option should be selected by SysTick-based drivers so that the
31 bool "Cortex-M SYSTICK timer with sys_clock_cycle_get_64() support"
36 This driver, due to its limited 24-bits hardware counter, is already
38 count a 64-bits value to support sys_clock_cycle_get_64().
/Zephyr-latest/drivers/gpio/
DKconfig.cmsdk_ahb1 # ARM CMSDK (Cortex-M System Design Kit) AHB GPIO cfg
4 # SPDX-License-Identifier: Apache-2.0
7 bool "ARM CMSDK (Cortex-M System Design Kit) AHB GPIO Controllers"
/Zephyr-latest/arch/arm/core/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
29 This option signifies the use of a CPU of the Cortex-M family.
44 This option signifies the use of a CPU of the Cortex-R family.
61 # GDBSTUB has not yet been tested on Cortex M or R SoCs
66 This option signifies the use of a CPU of the Cortex-A family.
69 # GDB for ARM expects up to 18 4-byte plus 8 12-byte
70 # registers - 336 HEX letters
76 From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
78 Thumb-2 technology is the instruction set underlying the ARM Cortex
83 Thumb-2 technology builds on the success of Thumb, the innovative
[all …]
/Zephyr-latest/dts/bindings/cpu/
Darm,cortex-m55.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M55 CPU
6 compatible: "arm,cortex-m55"
8 include: arm,cortex-m.yaml
Darm,cortex-m55f.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M55F CPU
6 compatible: "arm,cortex-m55f"
8 include: arm,cortex-m.yaml
Darm,cortex-m23.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M23 CPU
6 compatible: "arm,cortex-m23"
8 include: arm,cortex-m.yaml
Darm,cortex-m3.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M3 CPU
6 compatible: "arm,cortex-m3"
8 include: arm,cortex-m.yaml
Darm,cortex-m33.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M33 CPU
6 compatible: "arm,cortex-m33"
8 include: arm,cortex-m.yaml
Darm,cortex-m33f.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M33F CPU
6 compatible: "arm,cortex-m33f"
8 include: arm,cortex-m.yaml
Darm,cortex-m4.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M4 CPU
6 compatible: "arm,cortex-m4"
8 include: arm,cortex-m.yaml
Darm,cortex-m4f.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M4F CPU
6 compatible: "arm,cortex-m4f"
8 include: arm,cortex-m.yaml
Darm,cortex-m7.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M7 CPU
6 compatible: "arm,cortex-m7"
8 include: arm,cortex-m.yaml
Darm,cortex-m85.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M85 CPU
6 compatible: "arm,cortex-m85"
8 include: arm,cortex-m.yaml
Darm,cortex-m85f.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M85F CPU
6 compatible: "arm,cortex-m85f"
8 include: arm,cortex-m.yaml
Darm,cortex-m1.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M1 CPU
6 compatible: "arm,cortex-m1"
8 include: arm,cortex-m.yaml
/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst3 Arm Cortex-M Developer Guide
9 This page contains detailed information about the status of the Arm Cortex-M
11 developing Zephyr applications for Arm Cortex-M-based platforms.
17 Arm Cortex-M implementation variants.
20 …---------------------------------+-----------------------------------+-----------------+---------+…
22 …---------------------------------+-----------------------------------+-----------------+---------+…
23 … | Arm v6-M | Arm v7-M | Arm v8-M …
24 …---------------------------------+-----------------------------------+-----------------+---------+…
26 …---------------------------------+-----------------------------------+-----------------+---------+…
28 …---------------------------------+-----------------------------------+-----------------+---------+…
[all …]
/Zephyr-latest/boards/toradex/verdin_imx8mp/doc/
Dindex.rst7 i.MX 8M Plus family of processors (or System on Chips - SoCs).
11 +-------------------------------------------------+-----------------------+
14 | Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
15 +-------------------------------------------------+-----------------------+
16 | Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
17 +-------------------------------------------------+-----------------------+
18 | Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad |
19 +-------------------------------------------------+-----------------------+
20 | Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad |
21 +-------------------------------------------------+-----------------------+
[all …]
/Zephyr-latest/tests/kernel/common/
Dmultilib.txt8 (for example, ARM Cortex-M requires thumb2 multilib and will be broken with
9 default ("arm") multilib or "thumb" multilib). This app is a smoke-test
10 for selecting non-wrong multilib - it uses operation(s) which guaranteedly
13 Sample failure output ("thumb" used on Cortex-M instead of "thumb2"):
/Zephyr-latest/dts/bindings/timer/
Darm,armv8.1m-systick.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARMv8.1-M System Tick
6 compatible: "arm,armv8.1m-systick"
8 include: [cortex-m-systick.yaml]
/Zephyr-latest/samples/subsys/debug/debugmon/
DREADME.rst1 .. zephyr:code-sample:: debugmon
4 Configure the Debug Monitor feature on a Cortex-M processor.
17 .. _debugmon-sample-requirements:
24 #. Support Debug Monitor feature (available on Cortex-M processors with the exception of Cortex-M0)
34 .. zephyr-app-commands::
35 :zephyr-app: samples/subsys/debug/debugmon
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Dm33.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
9 /* Model in the device tree a Cortex-M33 core being 'plugged' into each
13 compatible = "arm,cortex-m33";
17 compatible = "arm,cortex-m33";
21 arm,num-irq-priority-bits = <4>;

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