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/Zephyr-Core-3.6.0/arch/arm/core/cortex_a_r/
DKconfig117 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
118 The Armv7-R architecture implements a traditional Arm architecture with
119 multiple modes and supports a Protected Memory System Architecture
138 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
139 The Armv8-R architecture targets at the Real-time profile. It introduces
141 Protected Memory System Architecture (PMSA) based on a Memory Protection
/Zephyr-Core-3.6.0/scripts/tests/twister/
Dtest_quarantine.py23 ['dummy architecture', 'another architecture'],
31 ['dummy architecture', 'another architecture'],
39 ['all', 'another architecture'],
221 'scenario, platform, architecture, simulation, expected_idx',
234 architecture, argument
265 architecture=architecture,
272 architecture=architecture,
/Zephyr-Core-3.6.0/arch/
DKconfig1 # General architecture configuration options
14 # Architecture symbols
26 ARC architecture
38 ARM architecture
52 ARM64 (AArch64) architecture
59 MIPS architecture
72 SPARC architecture
93 x86 architecture
102 Nios II Gen 2 architecture
118 RISCV architecture
[all …]
/Zephyr-Core-3.6.0/doc/services/dsp/
Dindex.rst10 The DSP API provides an architecture agnostic way for signal processing.
11 Currently, the API will work on any architecture but will likely not be
15 Architecture Status
44 Optimizing for your architecture
47 If your architecture is showing as ``Unoptimized``, it's possible to add a new
53 linked in at :file:`subsys/dsp/CMakeLists.txt`. To add architecture-specific attributes,
/Zephyr-Core-3.6.0/doc/hardware/porting/
Darch.rst3 Architecture Porting Guide
6 An architecture port is needed to enable Zephyr to run on an :abbr:`ISA
7 (instruction set architecture)` or an :abbr:`ABI (Application Binary
20 An architecture port can be divided in several parts; most are required and
23 * **The early boot sequence**: each architecture has different steps it must
26 * **Interrupt and exception handling**: each architecture handles asynchronous
33 and architecture-dependent, and thread abortion possibly as well (required).
36 controller are tied to the architecture (some required, some optional).
39 architecture-specific implementation for performance reasons (required).
44 * **Fault management**: for implementing architecture-specific debug help and
[all …]
/Zephyr-Core-3.6.0/include/zephyr/arch/arm/
Dstructs.h12 /* Per CPU architecture specifics */
19 /* Default definitions when no architecture specific definitions exist. */
21 /* Per CPU architecture specifics (empty) */
/Zephyr-Core-3.6.0/samples/net/dsa/
DREADME.rst2 :name: DSA (Distributed Switch Architecture)
5 Test and debug Distributed Switch Architecture
10 Example on testing/debugging Distributed Switch Architecture
/Zephyr-Core-3.6.0/kernel/include/
Dkernel_arch_interface.h9 * @brief Internal kernel APIs implemented at the architecture layer.
11 * Not all architecture-specific defines are here, APIs that are used
30 * @defgroup arch-timing Architecture timing APIs
35 * Architecture-specific implementation of busy-waiting
45 * @defgroup arch-threads Architecture thread APIs
88 * by the architecture. It is the same data structure stored in the
123 * architecture code to assume that it has any particular value at any
181 * @note For ARM architecture, disabling floating point preservation may only
195 * This API depends on each architecture implimentation. If the architecture
202 * @param options architecture dependent options
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/Zephyr-Core-3.6.0/arch/posix/core/
Dposix_core_nsi.c10 * This posix architecture "bottom" will be used when building with the native simulator.
18 * Initialize the posix architecture
27 * Clear the state of the POSIX architecture
/Zephyr-Core-3.6.0/arch/arm/core/
Delf.c14 * @brief Architecture specific function for relocating partially linked (static) elf
17 * instructions are architecture specific and each architecture supporting extensions
/Zephyr-Core-3.6.0/drivers/ethernet/
DKconfig.dsa1 # Distributed Switch Architecture [DSA] configuration options
8 bool "Distributed Switch Architecture support"
11 Enable Distributed Switch Architecture support. For now it
/Zephyr-Core-3.6.0/boards/posix/doc/
Darch_soc.rst3 The POSIX architecture
14 The POSIX architecture, in combination with the inf_clock SOC layer,
15 provides the foundation, architecture and SOC layers for a set of virtual test
22 Zephyr application, eliminating the need for architecture-specific
27 The POSIX architecture is not related and should not be confused with the
61 The POSIX architecture is known to **not** work on macOS due to
97 `Rationale for this port`_ and :ref:`Architecture<posix_arch_architecture>`
177 Currently, these are the most significant features which are not supported in this architecture:
188 :ref:`the architecture section's architecture layer paragraph <posix_arch_design_archl>`
240 This native port compiles your code directly for the host architecture
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Dbsim_boards_design.rst16 This page covers the design, architecture and rationale, of the
20 These boards use the `native simulator`_ and the :ref:`POSIX architecture<Posix arch>` to build
72 With the POSIX architecture we provided an overall
112 The :ref:`native_sim <native_sim>` board shares the :ref:`POSIX architecture<Posix arch>`,
130 The basic architecture layering of these boards is as follows:
133 - The architecture, SOC and board components of Zephyr are replaced with
135 - The architecture (arch) is the Zephyr :ref:`POSIX architecture<Posix arch>`
139 - The POSIX architecture provides an adaptation from the Zephyr arch API
142 See :ref:`POSIX arch architecture<posix_arch_architecture>`
167 Overall architecture in a Zephyr application in an embedded target vs a bsim
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/Zephyr-Core-3.6.0/arch/xtensa/core/
Delf.c23 * @brief Architecture specific function for relocating shared elf
26 * These relocation instructions are architecture specific and each architecture
/Zephyr-Core-3.6.0/doc/services/pm/
Doverview.rst5 are designed to be architecture and SOC independent. This enables power
9 The architecture and SOC independence is achieved by separating the core
/Zephyr-Core-3.6.0/subsys/testsuite/arch/unit_testing/
DKconfig11 The unit_testing architecture identifies itself as X86 for basic
21 The unit testing architecture is expected to always have access to a
/Zephyr-Core-3.6.0/arch/arm64/core/
DKconfig201 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
202 The Armv8-A architecture introduces the ability to use 64-bit and
208 compatibility with the Armv7-A architecture and enhances that profile
227 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
228 The Armv8-R architecture targets at the Real-time profile. It introduces
230 Protected Memory System Architecture (PMSA) based on a Memory Protection
Dcoredump.c10 /* Identify the version of this block (in case of architecture changes).
11 * To be interpreted by the target architecture specific block parser.
15 /* Structure to store the architecture registers passed arch_coredump_info_dump
55 /* Target architecture information header */ in arch_coredump_info_dump()
/Zephyr-Core-3.6.0/doc/services/debugging/
Dcoredump.rst60 4. Start the debugger corresponding to the target architecture.
227 architecture-specific block, and multiple memory blocks. All numbers in
253 - Indicate which target (e.g. architecture or SoC) so the parser
269 Architecture-specific Block
272 The architecture-specific block contains the byte stream of data specific
273 to the target architecture (e.g. CPU registers)
275 .. list-table:: Architecture-specific Block
284 - ``A`` to indicate this is a architecture-specific block.
288 architecture specific block parser.
296 - Contains target architecture specific data.
[all …]
/Zephyr-Core-3.6.0/include/zephyr/arch/
Dstructs.h8 * The purpose of this file is to provide essential/minimal architecture-
34 /* Default definitions when no architecture specific definitions exist. */
36 /* Per CPU architecture specifics (empty) */
/Zephyr-Core-3.6.0/include/zephyr/
Dfatal.h31 * Invokes architecture-specific code to power off or halt the system in
45 * unconditionally. Depending on architecture support, this may be
70 * Called by architecture code upon a fatal error.
72 * This function dumps out architecture-agnostic information about the error
/Zephyr-Core-3.6.0/doc/kernel/services/other/
Dfloat.rst12 the Intel x86 architecture, the SPARC architecture and ARCv2 SoCs
14 are architecture specific.
59 floating point registers. Depending upon the underlying CPU architecture,
75 ARM Cortex-M architecture (with the Floating Point Extension)
82 On the ARM Cortex-M architecture with the Floating Point Extension, the kernel
118 architecture, minimizing interrupt latency, when the floating
136 ARM64 architecture
145 On the ARM64 (Aarch64) architecture the kernel treats each thread as a FPU
162 ARCv2 architecture
165 On the ARCv2 architecture, the kernel treats each thread as a non-user
[all …]
/Zephyr-Core-3.6.0/.github/workflows/
Ddo_not_merge.yml11 contains(github.event.*.labels.*.name, 'Architecture Review') ||
18 echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'."
/Zephyr-Core-3.6.0/doc/security/
Dsecurity-overview.rst26 1. **Secure Development:** Defines the system architecture and
31 to enforce them. A security architecture of the system and
100 scoped for future releases. The Zephyr runtime architecture is a
139 The security architecture is based on a monolithic design where the
246 software security. Furthermore, a system architecture document shall be
249 System Architecture
252 .. figure:: media/security-zephyr-system-architecture.png
254 Figure 2: Zephyr System Architecture
256 A high-level schematic of the Zephyr system architecture is given in
257 Figure 2. It separates the architecture into an OS part (*kernel + OS
[all …]
/Zephyr-Core-3.6.0/arch/arm64/
DKconfig1 # ARM64 architecture configuration options
28 When this option is selected, the architecture interrupt control

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