Searched +full:81 +full:ms (Results 1 – 10 of 10) sorted by relevance
148 * RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc188 10 d8 00 ff 82 41 bd 00 81 e5 7b c6 44 03 67 38
446 …"10/10 [==============================] - 1s 47ms/step - loss: 0.7289 - mae: 0.7120 - val_loss: 0.…448 …"10/10 [==============================] - 0s 6ms/step - loss: 0.6329 - mae: 0.6488 - val_loss: 0.5…450 …"10/10 [==============================] - 0s 6ms/step - loss: 0.5201 - mae: 0.5735 - val_loss: 0.5…452 …"10/10 [==============================] - 0s 6ms/step - loss: 0.5057 - mae: 0.5760 - val_loss: 0.4…454 …"10/10 [==============================] - 0s 5ms/step - loss: 0.4502 - mae: 0.5459 - val_loss: 0.4…456 …"10/10 [==============================] - 0s 6ms/step - loss: 0.4168 - mae: 0.5332 - val_loss: 0.4…458 …"10/10 [==============================] - 0s 6ms/step - loss: 0.4211 - mae: 0.5341 - val_loss: 0.4…460 …"10/10 [==============================] - 0s 6ms/step - loss: 0.3988 - mae: 0.5287 - val_loss: 0.4…462 …"10/10 [==============================] - 0s 5ms/step - loss: 0.3901 - mae: 0.5230 - val_loss: 0.4…464 …"10/10 [==============================] - 0s 5ms/step - loss: 0.3804 - mae: 0.5179 - val_loss: 0.3…[all …]
12 …EROFS -31=EMLINK -32=EPIPE -33=EDEADLK -34=ENOLCK -35=ENOTSUP -36=EMSGSIZE -72=ECANCELED -81=ERRMAX102 95 k_sleep msec=%u ms | Returns %u103 96 k_msleep msec=%u ms | Returns %u
1168 #define TLS_RECORD_OVERHEAD 811187 /* Wait for ACK (empty window, min. 100 ms due to silly window in ZTEST()1280 /* Wait for ACK (empty window, min. 100 ms due to silly window in ZTEST()1383 zassert_true(time_diff >= 500, "Expected timeout after 500ms but " in ZTEST()1438 zassert_true(time_diff >= 500, "Expected timeout after 500ms but " in ZTEST()1638 /* Wait for ACK (empty window, min. 100 ms due to silly window in ZTEST()
1290 * The count number of the counter for 25 ms register.1291 * The 25 ms register is calculated by (count number *1.024 kHz).1294 #define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */1620 /* 0x50: Port 80h/81h Status Register */1624 /* 0x52: Port 81h Data Register */1678 /* Accept Port 81h Cycle */
23 xtal-enable-delay-ms = <300>;24 pll-lock-timeout-ms = <30>;716 interrupts = <81 0>;
138 /* using maximum erase time(ms) for 4K page, since344 interrupts = <80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
172 /* maximum erase time(ms) for a 8K sector */842 80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
75 * But less that 1.5ms (EVENT_OVERHEAD_XTAL_US) (ULL to LLL time offset).1325 * 06 1f f3 88 81 e7 bd 94 c9 c3 69 b9 a6 68 46 in radio_ccm_tx_pkt_set_ut()
4 …ms+htvX7zBAQwZjZhMyoO9sgGCxsSn2IA000DEWVCL/rtXLUCkxFMAg653XZIUToUNdIzt6kz2uMrzvOG7/h0Soa7dX0x+eNBK…
