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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dpll_hsi_fracn_550.overlay30 clock-frequency = <DT_FREQ_M(550)>;
Dpll_hse_550.overlay30 clock-frequency = <DT_FREQ_M(550)>;
/Zephyr-latest/dts/bindings/led_strip/
Dws2812.yaml16 at least 550 ns, with 700 ns or so typical. Pixel order is GRB.
/Zephyr-latest/modules/hal_nordic/nrf_802154/sl_opensource/platform/
Dnrf_802154_clock_zephyr.c82 #define MAX_HFXO_RAMP_UP_TIME_US 550
/Zephyr-latest/dts/bindings/auxdisplay/
Dhit,hd44780.yaml68 default: 550
/Zephyr-latest/boards/st/nucleo_h723zg/
Dnucleo_h723zg.dts113 clock-frequency = <DT_FREQ_M(550)>;
/Zephyr-latest/boards/st/stm32h735g_disco/
Dstm32h735g_disco.dts93 clock-frequency = <DT_FREQ_M(550)>;
/Zephyr-latest/boards/st/nucleo_h723zg/doc/
Dindex.rst53 - 550 MHz max CPU frequency
143 driven by the PLL clock at 550MHz, driven by an 8MHz high-speed external clock.
/Zephyr-latest/doc/_doxygen/
Dlogo.svg13 height="550">
/Zephyr-latest/doc/_static/images/
Dlogo.svg13 height="550">
/Zephyr-latest/doc/connectivity/bluetooth/img/
Dl2cap_b_frame.drawio.svg4 …125 400 137.5 400 L 143.75 400 Q 150 400 150 425 L 150 525 Q 150 550 162.5 550 L 175 550" fill="no…
Dl2cap_k_frame.drawio.svg4 …125 400 137.5 400 L 143.75 400 Q 150 400 150 425 L 150 525 Q 150 550 162.5 550 L 175 550" fill="no…
Dl2cap_k_frame_1.drawio.svg4 …125 400 137.5 400 L 143.75 400 Q 150 400 150 425 L 150 525 Q 150 550 162.5 550 L 175 550" fill="no…
/Zephyr-latest/boards/st/stm32h735g_disco/doc/
Dindex.rst97 is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock.
/Zephyr-latest/tests/bluetooth/host/cs/bt_le_cs_parse_pct/src/
Dmain.c87 {.input = {0x26, 0xA2, 0xC9}, .output = {.i = 550, .q = -870}}, in ZTEST()
/Zephyr-latest/include/zephyr/drivers/usb_c/
Dusbc_tc.h137 #define TC_T_TRY_TIMEOUT_MIN_MS 550
Dusbc_pd.h242 #define PD_T_SPR_PS_TRANSITION_MAX_MS 550
/Zephyr-latest/doc/connectivity/bluetooth/autopts/
Dautopts-linux.rst119 :width: 550
/Zephyr-latest/doc/build/cmake/
Dbuild-build-phase-2.svg4550 C 246 529.57 304.2 513 376 513 C 447.8 513 506 529.57 506 550 C 506 570.43 447.8 587 376 587 C…
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h7.c121 /* All h7 SoC with maximum 550MHz SYSCLK */
/Zephyr-latest/tests/benchmarks/latency_measure/
DREADME.rst103 …k - Add data to k_stack (w/ ctx switch) : 550 cycles , 4583 n…
/Zephyr-latest/doc/connectivity/networking/api/images/
Dlwm2m_engine_state_machine.svg4550 L 146.25 593.63" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="stro…
/Zephyr-latest/include/zephyr/sys/
Dutil_internal_util_dec.h571 #define Z_UTIL_DEC_551 550
Dutil_internal_util_inc.h569 #define Z_UTIL_INC_549 550
Dutil_internal_util_x2.h295 #define Z_UTIL_X2_275 550

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