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/Zephyr-latest/dts/bindings/gpio/
Dweact,dcmi-camera-connector.yaml9 (1) OV_STROBE (Unused) (2) AGND
10 3 DVP_SDA (4) AVDD-2V8
13 9 DVP_HSYNC (10) DVDD-1V5
14 (11) 2V8 12 DVP_D7
20 (23) AF-2V8 (24) GND
Drenesas,mipi-header.yaml11 1 GND IIC_SDA 14
18 8 GND 1V8 21
19 9 MIPI_CL_P 1V8 22
Dlinaro,96b-lscon-1v8.yaml6 compatible: "linaro,96b-lscon-1v8"
/Zephyr-latest/dts/bindings/interrupt-controller/
Darm,v8.1m-nvic.yaml1 description: ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)
3 compatible: "arm,v8.1m-nvic"
/Zephyr-latest/dts/arm/
Darmv8.1-m.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
18 #address-cells = <1>;
19 compatible = "arm,v8.1m-nvic";
26 compatible = "arm,armv8.1m-systick";
/Zephyr-latest/include/zephyr/arch/sparc/
Dsparc.h12 * @brief Definitions for the SPARC V8 architecture.
20 #define PSR_EF (1 << 12)
21 #define PSR_S (1 << 7)
22 #define PSR_PS (1 << 6)
23 #define PSR_ET (1 << 5)
/Zephyr-latest/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl.yaml31 gpio-voltage = "1p8";
35 gpio-voltage = "1v8";
43 pinmuxs = <&pinctrlb 1 IT8XXX2_ALT_FUNC_3>;
58 pinctrl-1 = <&uart1_rx_pb0_sleep &uart1_tx_pb1_sleep>;
98 - "1v8"
108 low level 1b: 4mA or 2mA
Dnxp,lpc-iocon-pinctrl.yaml26 IOCON_DIGIMODE=1,
32 IOCON_FILTEROFF=1
34 IOCON_EGP=1
35 IOCON_I2CFILTER=1
38 drive-open-drain: IOCON_OD=1
40 bias-pull-down: IOCON_MODE=1
87 1 SLEW_1- fast mode, output slew rate is faster
95 Set the pin to analog mode. Sets DIGIMODE=0, and ASW=1. Only valid for
106 - "1v8"
/Zephyr-latest/samples/boards/96boards/argonkey/microphone/
DREADME.rst18 This sample requires the ArgonKey board plus a USB to TTL 1V8 serial
45 A USB to TTL 1V8 serial cable may be attached to the low speed connector on
61 - 1 channel (mono), as only 1 microphone is available
/Zephyr-latest/boards/96boards/nitrogen/
D96b_lscon.dtsi9 compatible = "linaro,96b-lscon-1v8";
/Zephyr-latest/tests/arch/arm/arm_thread_swap/src/
Darm_thread_arch.c26 /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
32 * For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
58 .v5 = 0x56789abc, .v6 = 0x6789abcd, .v7 = 0x789abcde, .v8 = 0x89abcdef
84 "ldmia %0, {v1-v8};\n\t" in load_callee_saved_regs()
105 && (src->v8 == dst->v8), in verify_callee_saved()
115 src->v8, in verify_callee_saved()
123 dst->v8 in verify_callee_saved()
381 "push {v1-v8};\n\t" in alt_thread_entry()
384 "ldmia %0, {v1-v8};\n\t" in alt_thread_entry()
413 "pop {v1-v8};\n\t" in alt_thread_entry()
[all …]
/Zephyr-latest/boards/sifive/hifive_unleashed/
Dhifive_unleashed.dtsi25 compatible = "linaro,96b-lscon-1v8";
30 <23 0 &gpio0 1 0>, /* GPIO-B */
/Zephyr-latest/arch/sparc/core/
Dtrap_table_mvt.S8 * This file contains a full SPARC V8 trap table. The processor redirects
70 * Values in the range 0 to 0x5F that are not assigned in SPARC V8
71 * specification Table 7-1 are reserved for future versions of the
93 INTERRUPT_TRAP(1); ! 11 interrupt_level_1
102 INTERRUPT_TRAP(10); ! 1A interrupt_level_1
103 INTERRUPT_TRAP(11); ! 1B interrupt_level_11
104 INTERRUPT_TRAP(12); ! 1C interrupt_level_12
105 INTERRUPT_TRAP(13); ! 1D interrupt_level_13
106 INTERRUPT_TRAP(14); ! 1E interrupt_level_14
107 INTERRUPT_TRAP(15); ! 1F interrupt_level_15
[all …]
Dfatal.c20 * 1: 00000000 40004bf0 40008d30 40008c00
33 * #1 40002308 4000a1f8
76 * The SPARC V8 ABI guarantees that the stack pointer register
98 * Exception trap type (tt) values according to The SPARC V8
99 * manual, Table 7-1.
178 for (int i = 1; s && i < MAX_LOGLINES; i++) { in print_backtrace()
Dwindow_trap.S8 * This file contains standard handlers for the SPARC V8 window overflow and
30 /* l2 := WIM << (NWIN-1) */
31 sll %l3, (CONFIG_SPARC_NWIN-1), %l2
34 /* l3 := WIM >> 1 */
35 srl %l3, 1, %l3
37 /* WIM := (WIM >> 1) ^ (WIM << (NWIN-1)) */
51 /* l4 := WIM << 1 */
52 sll %l3, 1, %l4
53 /* l5 := WIM >> (NWIN-1) */
54 srl %l3, (CONFIG_SPARC_NWIN-1), %l5
[all …]
/Zephyr-latest/arch/arm/core/
Dfatal.c33 i + 1, (uint32_t)esf->fpu.s[i + 1], in esf_dump()
42 i + 1, (uint64_t)esf->fpu.d[i + 1], in esf_dump()
57 LOG_ERR("r10/v7: 0x%08x r11/v8: 0x%08x psp: 0x%08x", in esf_dump()
58 callee->v7, callee->v8, callee->psp); in esf_dump()
/Zephyr-latest/samples/boards/96boards/argonkey/sensors/
DREADME.rst58 A USB to TTL 1V8 serial cable may be attached to the low speed connector on
64 proxy: 1 ;
/Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_b_5_1.c10 * 'GATT_Test_Databases.xlsm' Sheet: 'Large Database 1'
25 * @brief UUID for the Value V8 Characteristic
51 * @brief Attribute read call back for the Value V8 attribute
73 * @brief Attribute write call back for the Value V8 attribute
/Zephyr-latest/arch/arc/core/
Dreset.S110 mov_s r1, 1
129 /* Set MPU (v4 or v8) registers to default */
148 add_s r2, r2, 1
164 #if defined(CONFIG_SMP) || CONFIG_MP_MAX_NUM_CPUS > 1
172 #if CONFIG_MP_MAX_NUM_CPUS == 1
173 kflag 1
/Zephyr-latest/boards/gaisler/generic_leon3/doc/
Dindex.rst43 JTAG chain (1): EP3C120/EP4CE115
48 LEON3 SPARC V8 Processor Cobham Gaisler
98 icache: 1 * 4 KiB, 16 bytes/line (4 KiB total)
99 dcache: 1 * 4 KiB, 16 bytes/line (4 KiB total)
100 Allocated 4096 KiB SRAM memory, in 1 bank at 0x40000000
101 Allocated 32 MiB SDRAM memory, in 1 bank at 0x60000000
/Zephyr-latest/include/zephyr/arch/arm/
Dthread.h33 uint32_t v8; /* r11 */ member
90 * +-bits 4-7-----bit-3----------bit-2--------bit-1---+----bit-0------+
96 * byte 1
140 #define Z_ARM_MODE_MPU_GUARD_FLOAT_Msk (1 << 3)
/Zephyr-latest/boards/firefly/roc_rk3568_pc/doc/
Dindex.rst11 RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture,
21 - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD)
36 - 1x Power status LED
117 I/TC: Secondary CPU 1 initializing
118 I/TC: Secondary CPU 1 switching to normal world boot
123 Secondary CPU core 1 (MPID:0x100) is up
128 thread_b: Hello World from cpu 1 on roc_rk3568_pc!
130 thread_b: Hello World from cpu 1 on roc_rk3568_pc!
/Zephyr-latest/samples/subsys/smf/smf_calculator/src/
Dmain.c20 K_MSGQ_DEFINE(output_msgq, CALCULATOR_STRING_LENGTH, 2, 1);
65 [BUTTON_1] = {.label = "1", .event = {.event_id = DIGIT_1_9, .operand = '1'}},
80 * LVGL v8.4 is not thread safe, so use a msgq to pass updates back
183 while (1) { in main()
/Zephyr-latest/boards/adi/max32690evkit/doc/
Dindex.rst34 - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON)
53 - Up To Four 1Mbaud UARTs with Flow Control
54 - Up To Two 1MHz I2C Master/Slave
56 - Eight External Channel, 12-bit 1MSPS SAR ADC w/ on-die temperature sensor
62 - 1-Wire Master
139 | | | | 1-2 | | | Connects external voltage reference to VREF pin, m…
146 | | | | 2-1 | | | Connects VDDIO (1V8) to I2C0 pull-up resistors. …
155 | | | | 1-2 | | | Connects pull-up to I2C0A_SDA (P2.7) sourced by I2…
162 | | | | 1-2 | | | Connects pull-up to I2C0A_SCL (P2.8) sourced by I2…
169 | | | | 1-2 | | | Connects red LED D1 to P0.14. …
[all …]
/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst23 … | Arm v6-M | Arm v7-M | Arm v8-M | Arm v8.1-M |
174 Stack limit checking (Arm v8-M)
177 Armv8-M and Armv8.1-M variants support stack limit checking using the MSPLIM and PSPLIM
193 Stack overflows trigger the dedicated UsageFault exception provided by Arm v8-M.
276 will set the PRIMASK register to 1, eventually, masking all IRQs with configurable
415 the stack guard (in certain Arm v8-M configurations with :kconfig:option:`CONFIG_MPU_GAP_FILLING`
420 * When :kconfig:option:`CONFIG_HW_STACK_PROTECTION` is enabled on Arm v8-M platforms the native
442 …ption to this setting is when :kconfig:option:`CONFIG_MPU_GAP_FILLING` is disabled (Arm v8-M only);
515 In Arm v8-M processors the MPU architecture does not allow programmed MPU regions to
660 …Arm v6-M | Arm v7-M | Arm v8-M | Arm v8.1-M …

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