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/Zephyr-latest/tests/drivers/can/api/src/
Dcommon.c5 * SPDX-License-Identifier: Apache-2.0
26 * @brief Standard (11-bit) CAN ID frame 1.
36 * @brief Standard (11-bit) CAN ID frame 2.
46 * @brief Extended (29-bit) CAN ID frame 1.
56 * @brief Extended (29-bit) CAN ID frame 1.
66 * @brief Standard (11-bit) CAN ID RTR frame 1.
76 * @brief Extended (29-bit) CAN ID RTR frame 1.
87 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
94 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
101 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
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/Zephyr-latest/dts/bindings/serial/
Dst,stm32-uart-base.yaml2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
8 - name: uart-controller.yaml
9 property-blocklist:
10 - clock-frequency
11 - name: pinctrl-device.yaml
12 - name: reset-device.yaml
13 - name: uart-controller-pin-inversion.yaml
28 single-wire:
31 Enable the single wire half-duplex communication.
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/Zephyr-latest/dts/bindings/counter/
Despressif,esp32-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Espressif's general-purpose Timers.
7 is SoC-dependent.
32 - 0
33 - 1
41 - 0
42 - 1
51 Values above that range will be 16-bit-masked. Values 0 and 1 will be
56 compatible: "espressif,esp32-timer"
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_interrupt.h3 * SPDX-License-Identifier: Apache-2.0
28 #define ACE_INTL_I3C 16
43 * provides per-core masking and status checking: ACE_DINT is an array
46 * bit to discriminate sources (e.g. TTS's bits 0-2 are
66 uint16_t is[32]; /* status (potentially masked by ie) */
68 uint32_t unused[16];
72 * each host inter-processor communication capability instance in a single register.
84 #define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1)
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_interrupt.h3 * SPDX-License-Identifier: Apache-2.0
26 #define ACE_INTL_I3C 16
41 * provides per-core masking and status checking: ACE_DINT is an array
44 * bit to discriminate sources (e.g. TTS's bits 0-2 are
64 uint16_t is[32]; /* status (potentially masked by ie) */
66 uint32_t unused[16];
70 * each host inter-processor communication capability instance in a single register.
82 #define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1)
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Dadsp_interrupt.h3 * SPDX-License-Identifier: Apache-2.0
26 #define ACE_INTL_I3C 16
41 * provides per-core masking and status checking: ACE_DINT is an array
44 * bit to discriminate sources (e.g. TTS's bits 0-2 are
64 uint16_t is[32]; /* status (potentially masked by ie) */
66 uint32_t unused[16];
70 * each host inter-processor communication capability instance in a single register.
82 #define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1)
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc_msi.c4 * SPDX-License-Identifier: Apache-2.0
14 /* Helper macro to read 64-bit data using two 32-bit data read */
22 * Configure capability of generating 16 messages, in iproc_pcie_msix_config()
23 * MSI-X Table offset 0x10000 on BAR2, in iproc_pcie_msix_config()
24 * MSI-X PBA offset 0x10800 on BAR2. in iproc_pcie_msix_config()
26 pcie_ep_conf_write(dev, MSIX_CONTROL, (MSIX_TABLE_SIZE - 1)); in iproc_pcie_msix_config()
35 /* Configure capability of generating 16 messages */ in iproc_pcie_msi_config()
72 const struct iproc_pcie_ep_config *cfg = dev->config; in iproc_pcie_generate_msi()
74 pcie_write32(msi_num, &cfg->base->paxb_pcie_sys_msi_req); in iproc_pcie_generate_msi()
136 struct iproc_pcie_ep_ctx *ctx = dev->data; in generate_pending_msix()
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/Zephyr-latest/drivers/gpio/
Dgpio_pcal64xxa.c5 * SPDX-License-Identifier: Apache-2.0
78 pcal64xxa_data_t masked; member
131 struct pcal64xxa_drv_data *drv_data = dev->data; in pcal64xxa_pin_configure()
132 const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; in pcal64xxa_pin_configure()
137 LOG_DBG("%s: configure pin %i with flags 0x%08X", dev->name, pin, flags); in pcal64xxa_pin_configure()
139 /* This device does not support open-source outputs, and open-drain in pcal64xxa_pin_configure()
140 * outputs can be only configured port-wise. in pcal64xxa_pin_configure()
143 return -ENOTSUP; in pcal64xxa_pin_configure()
151 return -ENOTSUP; in pcal64xxa_pin_configure()
155 return -EWOULDBLOCK; in pcal64xxa_pin_configure()
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/Zephyr-latest/arch/x86/core/ia32/
Dcrt0.S2 * Copyright (c) 2010-2015 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Crt0 module for the IA-32 boards
72 /* IA32_EFER NXE bit set */
87 /* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */
98 /* We are now executing in virtual memory. We'll un-map the identity
110 /* Enable write-back caching by clearing the NW and CD bits */
128 /* load 32-bit operand size GDT */
159 * Note that all floating point exceptions are masked by default,
174 * Note that all SSE exceptions are masked by default,
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/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c5 * SPDX-License-Identifier: Apache-2.0
30 * between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
34 * We touch the Cortex-M's primary mask and base priority registers
72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
73 pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY; in z_power_soc_deep_sleep()
74 pcr->OSC_ID = pcr->SYS_SLP_CTRL; in z_power_soc_deep_sleep()
86 * PM post ops. This de-asserts peripheral SLP_EN signals. in z_power_soc_deep_sleep()
88 pcr->SYS_SLP_CTRL = 0U; in z_power_soc_deep_sleep()
89 SCB->SCR &= ~BIT(2); in z_power_soc_deep_sleep()
92 htmr0->PRLD = 0U; /* make sure its stopped */ in z_power_soc_deep_sleep()
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/Zephyr-latest/include/zephyr/xen/public/
Dxen.h1 /* SPDX-License-Identifier: MIT */
33 #include "arch-arm.h"
110 #define __HYPERVISOR_event_channel_op_compat 16
178 * DOMID_IO is used to restrict page-table updates to mapping I/O memory.
182 * aren't adjusted on the I/O-mapping code path).
194 * - HYPERVISOR_mmu_update()'s, HYPERVISOR_mmuext_op()'s, or
196 * - with XENMAPSPACE_gmfn_foreign,
221 * Event channel endpoints per domain (when using the 2-level ABI):
231 * looking for changes to 'version'. If the least-significant bit of
245 * ((((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul) >> 32)
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_loapic.c2 * Copyright (c) 1984-2008, 2011-2015 Wind River Systems, Inc.
3 * SPDX-License-Identifier: Apache-2.0
34 #define LOAPIC_LVT_PENTIUM4 5 /* LO APIC LVT - Pentium4 */
35 #define LOAPIC_LVT_P6 4 /* LO APIC LVT - P6 */
36 #define LOAPIC_LVT_P5 3 /* LO APIC LVT - P5 */
54 /* Local APIC Spurious-Interrupt Register Bits */
59 #if CONFIG_LOAPIC_SPURIOUS_VECTOR_ID == -1
60 #define LOAPIC_SPURIOUS_VECTOR_ID (CONFIG_IDT_NUM_VECTORS - 1)
93 * in xAPIC and flat model, bits 24-31 in LDR (Logical APIC ID) are in z_loapic_enable()
103 * in X2APIC, LDR is read-only. in z_loapic_enable()
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/Zephyr-latest/soc/mediatek/mt8xxx/
Dsoc.c2 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/sys/libc-hooks.h>
39 * associated with one[1] of 16 "groups", each of which directs to a
50 * 0-5 0-5 1 (L1 is shared w/exceptions, poor choice)
51 * 6-7 7-8 1
52 * 8-10 9-11 2
53 * 11-13 16-18 3
75 * 16: UART_BT 36: PWR_ON_C0_IRQ 56: L2SRAM_SETERR
97 struct intc64 groups[16]; /* set bit == "member of group" */
98 struct intc64 group_status[16]; /* status, but masked by group */
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/Zephyr-latest/arch/arm/core/cortex_m/
Dirq_manage.c2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM Cortex-M interrupt management
49 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in arch_irq_is_enabled()
69 * run at a priority level which is not masked by irq_lock(). in z_arm_irq_priority_set()
77 /* Use caller supplied prio level as-is */ in z_arm_irq_priority_set()
86 * reduced set of priorities, like Cortex-M0/M0+). in z_arm_irq_priority_set()
88 __ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1), in z_arm_irq_priority_set()
90 prio - _IRQ_PRIO_OFFSET, irq, in z_arm_irq_priority_set()
91 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET)); in z_arm_irq_priority_set()
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/Zephyr-latest/subsys/net/lib/websocket/
Dwebsocket.c10 * SPDX-License-Identifier: Apache-2.0
84 int old_rc = atomic_inc(&ctx->refcount); in websocket_context_ref()
91 int old_rc = atomic_dec(&ctx->refcount); in websocket_context_unref()
94 return old_rc - 1; in websocket_context_unref()
102 return !!atomic_get(&ctx->refcount); in websocket_context_is_used()
160 rsp->data_len); in response_cb()
161 ctx->all_received = false; in response_cb()
164 rsp->data_len); in response_cb()
165 ctx->all_received = true; in response_cb()
175 struct websocket_context *ctx = req->internal.user_data; in on_header_field()
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/Zephyr-latest/include/zephyr/arch/nios2/
Dnios2.h4 /* SPDX-License-Identifier: Xnet */
61 * Functions for accessing select Nios II general-purpose registers.
100 * Low-level cache management functions
146 * type checking purposes. However if -O0 is used (i.e. CONFIG_DEBUG is on)
147 * we get errors "Control register number must be in range 0-31 for
155 * This compiles just fine with -Os.
187 * Bit masks & offsets for Nios II control registers.
189 * configuration. Bit masks for every possible field and the maximum size of
192 * All bit-masks are expressed relative to the position
193 * of the data with a register. To read data that is LSB-
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/Zephyr-latest/drivers/ethernet/phy/
Dphy_tja1103.c5 * SPDX-License-Identifier: Apache-2.0
33 /* MMD30 - Device status register */
35 #define TJA1103_DEVICE_CONTROL_GLOBAL_CFG_EN BIT(14)
36 #define TJA1103_DEVICE_CONTROL_SUPER_CFG_EN BIT(13)
37 /* Shared - PHY control register */
39 #define TJA1103_PHY_CONTROL_CFG_EN BIT(14)
40 /* Shared - PHY status register */
42 #define TJA1103_PHY_STATUS_LINK_STAT BIT(2)
44 /* Shared - PHY functional IRQ masked status register */
46 #define TJA1103_PHY_FUNC_IRQ_LINK_EVENT BIT(1)
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/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h4 * SPDX-License-Identifier: Apache-2.0
20 * must meet the alignment requirement of cortex-m4.
22 * 8/16/32 bits registers.
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
90 /* 0x102: High-Frequency Reference Divisor I */
92 /* 0x104: High-Frequency Reference Divisor F */
127 /* 0x008 - 0D: Power-Down Control 1 - 6 */
130 /* 0x020 - 21: Power-Down Control 1 - 2 */
133 /* 0x024: Power-Down Control 7 */
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/Zephyr-latest/arch/x86/core/intel64/
Duserspace.S4 * SPDX-License-Identifier: Apache-2.0
23 * 16 RFLAGS
40 pushq 16(%rdi) /* CS */
53 movq $0, -8(%rsp) /* Delete stashed RAX data */
67 * Current RFLAGS has been masked with ~X86_FMASK_MSR
75 * eventually gets put on the stack before we re-enable interrupts
76 * as this is a per-cpu and not per-thread area.
93 movq $0, -8(%rsp) /* Delete stashed RAX data */
109 sti /* re-enable interrupts */
111 /* call_id is in RAX. bounds-check it, must be less than
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/Zephyr-latest/drivers/i3c/
Di3c_mcux.c6 * SPDX-License-Identifier: Apache-2.0
125 * @brief Read a register and test for bit matches with timeout.
129 * @param reg Pointer to 32-bit Register.
131 * @param match Value to match for masked register value.
134 * @retval 0 If masked register value matches before time out.
135 * @retval -ETIMEDOUT Timedout without matching.
143 * quickly (some sub-microseconds) so no extra in reg32_poll_timeout()
147 return -ETIMEDOUT; in reg32_poll_timeout()
155 * @param reg Pointer to 32-bit Register.
171 * @brief Test if masked register value has certain value.
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/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dintel_adsp_hda.h2 * SPDX-License-Identifier: Apache-2.0
26 /* The read/write positions are masked to 24 bits */
41 #define DGCS_SCS BIT(31) /* Sample container size */
42 #define DGCS_GEN BIT(26) /* Gateway Enable */
43 #define DGCS_L1ETP BIT(25) /* L1 Enter Prevent */
44 #define DGCS_L1EXP BIT(24) /* L1 Exit Prevent */
45 #define DGCS_FWCB BIT(23) /* Firmware Control Buffer */
46 #define DGCS_GBUSY BIT(15) /* Gateway Busy */
47 #define DGCS_TE BIT(14) /* Transfer Error */
48 #define DGCS_BSC BIT(11) /* Buffer Segment Completion */
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/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2015-2021, Linaro Limited
11 * This file is exported by OP-TEE and is in kept in sync between secure
70 * Normal cached memory (write-back), shareable for SMP systems and not
78 * 32-bit registers.
86 * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b.
110 * Used by non-secure world to figure out which Trusted OS is installed.
113 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
123 * Used by non-secure world to figure out which version of the Trusted OS
127 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
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/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Minimum RX FIFO size in 32-bit words considering the largest used OUT packet
49 /* Default Rx FIFO size in 32-bit words calculated to support High-Speed with:
57 /* TX FIFO0 depth in 32-bit words (used by control IN endpoint)
61 #define UDC_DWC2_FIFO0_DEPTH (2 * 16U)
91 uint32_t diepctl[16];
92 uint32_t dieptsiz[16];
93 uint32_t diepdma[16];
94 uint32_t doepctl[16];
95 uint32_t doeptsiz[16];
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/Zephyr-latest/include/zephyr/net/
Dnet_ip.h10 * SPDX-License-Identifier: Apache-2.0
50 #define PF_LOCAL 6 /**< Inter-process communication */
51 #define PF_UNIX PF_LOCAL /**< Inter-process communication */
60 #define AF_LOCAL PF_LOCAL /**< Inter-process communication */
61 #define AF_UNIX PF_UNIX /**< Inter-process communication */
65 IPPROTO_IP = 0, /**< IP protocol (pseudo-val for setsockopt() */
94 /** @brief Convert 16-bit value from network to host byte order.
102 /** @brief Convert 32-bit value from network to host byte order.
110 /** @brief Convert 64-bit value from network to host byte order.
118 /** @brief Convert 16-bit value from host to network byte order.
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/Zephyr-latest/drivers/timer/
Dcortex_m_systick.c4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
27 * calls to elapsed() to read the COUNTFLAG bit. So it needs to be
29 * masked. Choosing a fraction of a tick is probably a good enough
32 #define MIN_DELAY MAX(1024U, ((uint32_t)CYC_PER_TICK/16U))
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
84 * case because the Cortex-m SysTick is not clocked in the low power
102 * re-program the SysTick.LOAD register, in sys_clock_set_timeout().
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