| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
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| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da.qsf | 1 # -------------------------------------------------------------------------- #
3 # Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
18 # -------------------------------------------------------------------------- #
21 # Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition
24 # -------------------------------------------------------------------------- #
37 # -------------------------------------------------------------------------- #
40 set_global_assignment -name FAMILY "MAX 10"
41 set_global_assignment -name DEVICE 10M50DAF484C6GES
42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48 APRIL 27, 2016"
[all …]
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| /Zephyr-latest/tests/lib/cmsis_dsp/statistics/src/ |
| D | q7.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
18 #define ABS_ERROR_THRESH_Q31 ((q31_t)(1 << 15))
37 DEFINE_TEST_VARIANT3(statistics_q7, arm_max_q7, 15, in_com1, 0, 15);
59 DEFINE_TEST_VARIANT3(statistics_q7, arm_min_q7, 15, in_com1, 0, 15);
81 DEFINE_TEST_VARIANT3(statistics_q7, arm_absmax_q7, 15, in_absminmax, 0, 15);
103 DEFINE_TEST_VARIANT3(statistics_q7, arm_absmin_q7, 15, in_absminmax, 0, 15);
115 ref[0] = ref_mean[ref_index]; in test_arm_mean_q7()
122 arm_mean_q7(input1, length, &output[0]); in test_arm_mean_q7()
137 DEFINE_TEST_VARIANT3(statistics_q7, arm_mean_q7, 15, in_com2, 0, 15);
[all …]
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
[all …]
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| /Zephyr-latest/boards/st/stm32l496g_disco/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map =
14 <0 0 &gpioc 4 0>, /* A0 */
15 <1 0 &gpioc 1 0>, /* A1 */
16 <2 0 &gpioc 3 0>, /* A2 */
17 <3 0 &gpiof 10 0>, /* A3 */
[all …]
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| /Zephyr-latest/dts/bindings/video/ |
| D | nxp,video-smartdma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,video-smartdma"
8 include: [base.yaml, pinctrl-device.yaml]
15 vsync-pin:
19 GPIO0 pin index to use for VSYNC input. Only pins 0-15 may be used.
20 hsync-pin:
24 GPIO0 pin index to use for HSYNC input. Only pins 0-15 may be used.
25 pclk-pin:
29 GPIO0 pin index to use for PCLK input. Only pins 0-15 may be used.
|
| /Zephyr-latest/dts/arm/microchip/ |
| D | mec172x_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 reg = <0x4000fc00 0x200>;
11 compatible = "microchip,xec-pcr";
12 reg = <0x40080100 0x100 0x4000a400 0x100>;
13 reg-names = "pcrr", "vbatr";
14 interrupts = <174 0>;
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
[all …]
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| /Zephyr-latest/boards/raytac/mdbt53_db_40/ |
| D | raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
19 low-power-enable;
25 psels = <NRF_PSEL(UART_TX, 0, 20)>,
26 <NRF_PSEL(UART_RX, 0, 22)>,
27 <NRF_PSEL(UART_RTS, 0, 19)>,
28 <NRF_PSEL(UART_CTS, 0, 21)>;
34 psels = <NRF_PSEL(UART_TX, 0, 20)>,
35 <NRF_PSEL(UART_RX, 0, 22)>,
36 <NRF_PSEL(UART_RTS, 0, 19)>,
37 <NRF_PSEL(UART_CTS, 0, 21)>;
[all …]
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| /Zephyr-latest/tests/subsys/dsp/utils/src/ |
| D | q15.c | 4 * SPDX-License-Identifier: Apache-2.0
24 (-32768, 0, -1.0F), (32767, 0, 0.999969482421875F), (32767, 15, 32767.0F), \
25 (-32768, 15, -32768.0F)
28 (-32768, 0, -1), (32767, 0, 0.999969482421875), (32767, 15, 32767.0), (-32768, 15, -32768.0)
35 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q15_to_f32()
44 "Conversion failed: 0x%08x shifted by %d = %f (expected %f)", data, shift, in test_shift_q15_to_f64()
|
| /Zephyr-latest/dts/bindings/phy/ |
| D | st,stm32u5-otghs-phy.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 This binding is to be used by the STM32U5xx transceivers which are built-in
9 compatible: "st,stm32u5-otghs-phy"
11 include: phy-controller.yaml
14 "#phy-cells":
15 const: 0
23 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
24 <&rcc STM32_SRC_HSE OTGHS_SEL(0)>;
27 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
31 clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
[all …]
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| /Zephyr-latest/tests/subsys/dsp/basicmath/src/ |
| D | q7.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
18 #define ABS_ERROR_THRESH_Q31 ((q31_t)(1 << 15))
45 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7, 15, in_com1, in_com2, ref_add, 15);
79 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_add_q7_in_place, 15, in_com1, in_com2, ref_add, 15);
114 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_sub_q7, 15, in_com1, in_com2, ref_sub, 15);
148 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_sub_q7_in_place, 15, in_com1, in_com2, ref_sub, 15);
183 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_mult_q7, 15, in_com1, in_com2, ref_mult, 15);
217 DEFINE_TEST_VARIANT4(basic_math_q7, zdsp_mult_q7_in_place, 15, in_com1, in_com2, ref_mult, 15);
249 DEFINE_TEST_VARIANT3(basic_math_q7, zdsp_negate_q7, 15, in_com1, ref_negate, 15);
[all …]
|
| /Zephyr-latest/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
15 * For example Message Channel 0 is configured as TX on core 0
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
21 * Message Channel 1 is configured as RX on core 0 and as TX
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
32 IPC_EVENT_BIT(0) | \
47 IPC_EVENT_BIT(15) \
52 [0] = BIT(0),
67 [15] = BIT(15),
[all …]
|
| /Zephyr-latest/boards/st/nucleo_h533re/ |
| D | st_morpho_connector.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
7 #include <zephyr/dt-bindings/gpio/st-morpho-header.h>
10 st_morpho_header: st-morpho-header {
11 compatible = "st-morpho-header";
12 #gpio-cells = <2>;
13 gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
14 gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
15 gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
16 <ST_MORPHO_L_2 0 &gpioc 11 0>,
[all …]
|
| /Zephyr-latest/dts/bindings/pwm/ |
| D | infineon,xmc4xxx-ccu4-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 dts/arm/infineon/xmc4xxx_xxx-pinctrl.dtsi
24 The pwm ccu4 node must define the slice-prescaler values and the pinctrl nodes:
26 slice-prescaler = <15 15 15 15>;
27 pinctrl-0 = <&pwm_out_p1_1_ccu40_ch2>;
28 pinctrl-names = "default";
34 pwms = <&pwm_ccu40 0 PWM_SEC(1) PWM_POLARITY_NORMAL>;
39 The pin should be configured with drive-push-pull bool option and hwctrl should be set
40 to disabled. The drive-strength field can be set to any of the supported values:
42 drive-strength = "strong-medium-edge";
[all …]
|
| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,ina219.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
16 Current LSB = max expected current [A] / 2^15
17 example: 100 -> ~3A
18 shunt-milliohm:
28 0 = 16 V FSR
31 The default of 32V is the power-on reset value of the device.
33 Should the expected bus voltage be below 16V set this to 0.
35 - 0
[all …]
|
| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | nxp,s32-siul2-eirq.yaml | 1 # Copyright 2022-2024 NXP
3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "nxp,s32-siul2-eirq"
9 include: [interrupt-controller.yaml, pinctrl-device.yaml, base.yaml]
15 pinctrl-0:
18 pinctrl-names:
21 filter-prescaler:
23 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
31 * IFCP is 0 to 15.
33 child-binding:
[all …]
|
| /Zephyr-latest/boards/shields/tcan4550evm/ |
| D | tcan4550evm.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
17 cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
19 tcan4x5x_tcan4550evm: can@0 {
21 reg = <0>;
22 /* reduced spi-max-frequency to accommodate flywire connections */
23 spi-max-frequency = <2000000>;
25 clock-frequency = <40000000>;
26 device-state-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 */
27 device-wake-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; /* D7 */
[all …]
|
| /Zephyr-latest/dts/bindings/power/ |
| D | nxp,s32-mc-rgm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,s32-mc-rgm"
14 func-reset-threshold:
16 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
17 default: 15
20 If the value of this property is 0, the Functional reset escalation
26 dest-reset-threshold:
28 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
29 default: 0
32 If the value of this property is 0, the Destructive reset escalation
[all …]
|
| /Zephyr-latest/boards/st/nucleo_h503rb/ |
| D | st_morpho_connector.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
7 #include <zephyr/dt-bindings/gpio/st-morpho-header.h>
10 st_morpho_header: st-morpho-header {
11 compatible = "st-morpho-header";
12 #gpio-cells = <2>;
13 gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
14 gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
15 gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
16 <ST_MORPHO_L_2 0 &gpioc 11 0>,
[all …]
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| /Zephyr-latest/boards/st/stm32l4r9i_disco/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 7 0>, /* A0 */
14 <1 0 &gpioc 4 0>, /* A1 */
15 <2 0 &gpioc 3 0>, /* A2 */
16 <3 0 &gpiob 0 0>, /* A3 */
17 <4 0 &gpioa 0 0>, /* A4 */
[all …]
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| /Zephyr-latest/boards/st/nucleo_l412rb_p/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 0 0>, /* A0 */
14 <1 0 &gpioa 1 0>, /* A1 */
15 <2 0 &gpioc 3 0>, /* A2 */
16 <3 0 &gpioc 2 0>, /* A3 */
17 <4 0 &gpioc 1 0>, /* A4 */
[all …]
|
| /Zephyr-latest/boards/st/nucleo_l433rc_p/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 0 0>, /* A0 */
14 <1 0 &gpioa 1 0>, /* A1 */
15 <2 0 &gpioc 3 0>, /* A2 */
16 <3 0 &gpioc 2 0>, /* A3 */
17 <4 0 &gpioc 1 0>, /* A4 */
[all …]
|
| /Zephyr-latest/boards/st/nucleo_l552ze_q/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
14 <1 0 &gpioa 2 0>, /* A1 */
15 <2 0 &gpioc 3 0>, /* A2 */
16 <3 0 &gpiob 0 0>, /* A3 */
17 <4 0 &gpioc 1 0>, /* A4 */
[all …]
|
| /Zephyr-latest/boards/st/nucleo_wba52cg/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 7 0>, /* A0 */
14 <1 0 &gpioa 6 0>, /* A1 */
15 <2 0 &gpioa 2 0>, /* A2 */
16 <3 0 &gpioa 1 0>, /* A3 */
17 <4 0 &gpioa 5 0>, /* A4 */
[all …]
|
| /Zephyr-latest/boards/st/nucleo_wba55cg/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 7 0>, /* A0 */
14 <1 0 &gpioa 6 0>, /* A1 */
15 <2 0 &gpioa 2 0>, /* A2 */
16 <3 0 &gpioa 1 0>, /* A3 */
17 <4 0 &gpioa 5 0>, /* A4 */
[all …]
|
