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/Zephyr-latest/modules/hal_nordic/nrfs/dvfs/
Dld_dvfs.c4 * SPDX-License-Identifier: Apache-2.0
45 LOG_DBG("REGW: NRF_ABB->TRIM.RINGO[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
47 (uint32_t)&NRF_ABB->TRIM.RINGO[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
48 opp_data->abb_ringo); in ld_dvfs_init()
49 LOG_DBG("REGW: NRF_ABB->TRIM.LOCKRANGE[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
51 (uint32_t)&NRF_ABB->TRIM.LOCKRANGE[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
52 opp_data->abb_lockrange); in ld_dvfs_init()
53 LOG_DBG("REGW: NRF_ABB->TRIM.PVTMONCYCLES[%d] 0x%x, V: 0x%x", in ld_dvfs_init()
55 (uint32_t)&NRF_ABB->TRIM.PVTMONCYCLES[CURR_TARG_ABB_SLOT], in ld_dvfs_init()
56 opp_data->abb_pvtmoncycles); in ld_dvfs_init()
[all …]
/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor_ll.h4 * SPDX-License-Identifier: Apache-2.0
14 #define CAD_INVALID -1
15 #define CAD_QSPI_ERROR -2
24 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
31 #define CAD_QSPI_CFG_BAUDDIV(x) FIELD_PREP(0x780000, x) argument
33 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
41 #define CAD_QSPI_DELAY_CSSOT(x) (FIELD_GET(0xff, (x)) << 0) argument
42 #define CAD_QSPI_DELAY_CSEOT(x) (FIELD_GET(0xff, (x)) << 8) argument
43 #define CAD_QSPI_DELAY_CSDADS(x) (FIELD_GET(0xff, (x)) << 16) argument
44 #define CAD_QSPI_DELAY_CSDA(x) (FIELD_GET(0xff, (x)) << 24) argument
[all …]
Dflash_cadence_nand_ll.h4 * SPDX-License-Identifier: Apache-2.0
16 (k_sem_take(&(param_ptr->interrupt_sem_t), K_FOREVER)), ())
18 #define CNF_GET_INIT_COMP(x) (FIELD_GET(BIT(9), x)) argument
19 #define CNF_GET_INIT_FAIL(x) (FIELD_GET(BIT(10), x)) argument
20 #define CNF_GET_CTRL_BUSY(x) (FIELD_GET(BIT(8), x)) argument
21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x)) argument
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x)) argument
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x)) argument
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x)) argument
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x)) argument
[all …]
/Zephyr-latest/drivers/sensor/ti/tmp108/
Dtmp108.h3 * Copyright (c) 2022 T-Mobile USA, Inc.
5 * SPDX-License-Identifier: Apache-2.0
47 #define TI_TMP108_MODE_SHUTDOWN(x) 0 argument
48 #define TI_TMP108_MODE_ONE_SHOT(x) (TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_SLEEP(x)) argument
49 #define TI_TMP108_MODE_CONTINUOUS(x) TI_TMP108_CONF_M1(x) argument
50 #define TI_TMP108_MODE_MASK(x) ~(TI_TMP108_CONF_M0(x) | \ argument
51 TI_TMP108_CONF_M1(x) | \
52 TI_TMP108_CONF_SLEEP(x))
54 #define TI_TMP108_FREQ_4_SECS(x) 0 argument
55 #define TI_TMP108_FREQ_1_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR0) argument
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dprci.h4 * SPDX-License-Identifier: Apache-2.0
25 #define ROSC_DIV(x) (((x) & 0x2F) << 0) argument
26 #define ROSC_TRIM(x) (((x) & 0x1F) << 16) argument
27 #define ROSC_EN(x) (((x) & 0x1) << 30) argument
28 #define ROSC_RDY(x) (((x) & 0x1) << 31) argument
30 #define XOSC_EN(x) (((x) & 0x1) << 30) argument
31 #define XOSC_RDY(x) (((x) & 0x1) << 31) argument
33 #define PLL_R(x) (((x) & 0x7) << 0) argument
35 #define PLL_F(x) (((x) & 0x3F) << 4) argument
36 #define PLL_Q(x) (((x) & 0x3) << 10) argument
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
31 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
46 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
58 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
60 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
100 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
101 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
[all …]
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
32 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
47 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
101 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
102 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
32 #define PCMSyCM_OFFSET(x) 0x16 + 0x4*(x) argument
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
39 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
54 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
96 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
97 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
98 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
[all …]
/Zephyr-latest/include/zephyr/toolchain/
Dxcc.h4 * SPDX-License-Identifier: Apache-2.0
11 #error Please do not include toolchain-specific headers directly, use <zephyr/toolchain.h> instead
52 #define __INT8_C(x) x argument
56 #define INT8_C(x) __INT8_C(x) argument
60 #define __UINT8_C(x) x ## U argument
64 #define UINT8_C(x) __UINT8_C(x) argument
68 #define __INT16_C(x) x argument
72 #define INT16_C(x) __INT16_C(x) argument
76 #define __UINT16_C(x) x ## U argument
80 #define UINT16_C(x) __UINT16_C(x) argument
[all …]
Dllvm.h4 * SPDX-License-Identifier: Apache-2.0
11 #error Please do not include toolchain-specific headers directly, use <zephyr/toolchain.h> instead
33 #define TOOLCHAIN_WARNING_SIZEOF_ARRAY_DECAY "-Wsizeof-array-decay"
65 #define __INT64_C(x) int_c(x, __int_least64_c_suffix__) argument
66 #define __UINT64_C(x) uint_c(x, __int_least64_c_suffix__) argument
68 #define __INT64_C(x) x argument
69 #define __UINT64_C(x) x ## U argument
86 #define __INT32_C(x) int_c(x, __int_least32_c_suffix__) argument
87 #define __UINT32_C(x) uint_c(x, __int_least32_c_suffix__) argument
89 #define __INT32_C(x) x argument
[all …]
/Zephyr-latest/lib/libc/minimal/include/
Dstdint.h6 * SPDX-License-Identifier: Apache-2.0
22 #define INT8_MIN (-INT8_MAX - 1)
23 #define INT16_MIN (-INT16_MAX - 1)
24 #define INT32_MIN (-INT32_MAX - 1)
25 #define INT64_MIN (-INT64_MAX - 1LL)
38 #define INT_FAST8_MIN (-INT_FAST8_MAX - 1)
39 #define INT_FAST16_MIN (-INT_FAST16_MAX - 1)
40 #define INT_FAST32_MIN (-INT_FAST32_MAX - 1)
41 #define INT_FAST64_MIN (-INT_FAST64_MAX - 1LL)
53 #define INT_LEAST8_MIN (-INT_LEAST8_MAX - 1)
[all …]
/Zephyr-latest/arch/nios2/core/
Dfatal.c4 * SPDX-License-Identifier: Apache-2.0
22 * TODO: Only caller-saved registers get saved upon exception in z_nios2_fatal_error()
26 LOG_ERR("Faulting instruction: 0x%08x", esf->instr - 4); in z_nios2_fatal_error()
27 LOG_ERR(" r1: 0x%08x r2: 0x%08x r3: 0x%08x r4: 0x%08x", in z_nios2_fatal_error()
28 esf->r1, esf->r2, esf->r3, esf->r4); in z_nios2_fatal_error()
29 LOG_ERR(" r5: 0x%08x r6: 0x%08x r7: 0x%08x r8: 0x%08x", in z_nios2_fatal_error()
30 esf->r5, esf->r6, esf->r7, esf->r8); in z_nios2_fatal_error()
31 LOG_ERR(" r9: 0x%08x r10: 0x%08x r11: 0x%08x r12: 0x%08x", in z_nios2_fatal_error()
32 esf->r9, esf->r10, esf->r11, esf->r12); in z_nios2_fatal_error()
33 LOG_ERR(" r13: 0x%08x r14: 0x%08x r15: 0x%08x ra: 0x%08x", in z_nios2_fatal_error()
[all …]
/Zephyr-latest/samples/subsys/zbus/msg_subscriber/
Dsample.yaml7 - CONFIG_ZBUS_LOG_LEVEL_DBG=y
12 - "^.*?I: ----> Publishing to acc_data_chan channel"
13 - "^.*?I: AL Memory allocated \\d{1,3} bytes. Total allocated \\d{1,3} bytes$"
14 - "^.*?I: FR Memory freed \\d{1,3} bytes. Total allocated 0 bytes$"
15 - "^.*?D: 0 -> bar_sub1"
16 - "^.*?D: 1 -> bar_msg_sub1"
17 - "^.*?D: 2 -> bar_msg_sub2"
18 - "^.*?D: 3 -> bar_msg_sub3"
19 - "^.*?D: 4 -> bar_msg_sub4"
20 - "^.*?D: 5 -> bar_msg_sub5"
[all …]
DREADME.rst1 .. zephyr:code-sample:: zbus-msg-subscriber
3 :relevant-api: zbus_apis
19 .. zephyr-app-commands::
20 :zephyr-app: samples/subsys/zbus/msg_subscriber
21 :host-os: unix
28 .. code-block:: console
30 -- west build: running target run
31 [0/1] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: qemu32,+nx,+pae
33 I: ----> Publishing to acc_data_chan channel
35 I: From listener foo_lis -> Acc x=1, y=10, z=100
[all …]
/Zephyr-latest/scripts/coccinelle/
Dnoderef.cocci9 // Options: --no-includes --include-headers
17 expression *x;
24 x = <+... sizeof(
25 - x
26 + *x
29 f(...,(T)(x),...,sizeof(
30 - x
31 + *x
35 - x
36 + *x
[all …]
/Zephyr-latest/drivers/sensor/ti/fdc2x1x/
Dfdc2x1x.h4 * SPDX-License-Identifier: Apache-2.0
61 #define FDC2X1X_REG_READ(x) (((x & 0xFF) << 1) | FDC2X1X_READ) argument
62 #define FDC2X1X_REG_WRITE(x) ((x & 0xFF) << 1) argument
63 #define FDC2X1X_TO_I2C_REG(x) ((x) >> 1) argument
67 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_SET(x) (((x) & 0x3) << 12) argument
68 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_GET(x) (((x) >> 12) & 0x3) argument
70 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_SET(x) ((x) & 0x1FF) argument
71 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_GET(x) (((x) >> 0) & 0x1FF) argument
74 #define FDC2X1X_STATUS_ERR_CHAN(x) (((x) >> 14) & 0x3) argument
75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1) argument
[all …]
/Zephyr-latest/arch/arm/core/
Dfatal.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Kernel fatal error handler for ARM Cortex-M and Cortex-R
11 * This module provides the z_arm_fatal_error() routine for ARM Cortex-M
12 * and Cortex-R CPUs.
23 LOG_ERR("r0/a1: 0x%08x r1/a2: 0x%08x r2/a3: 0x%08x", in esf_dump()
24 esf->basic.a1, esf->basic.a2, esf->basic.a3); in esf_dump()
25 LOG_ERR("r3/a4: 0x%08x r12/ip: 0x%08x r14/lr: 0x%08x", in esf_dump()
26 esf->basic.a4, esf->basic.ip, esf->basic.lr); in esf_dump()
27 LOG_ERR(" xpsr: 0x%08x", esf->basic.xpsr); in esf_dump()
29 for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) { in esf_dump()
[all …]
/Zephyr-latest/samples/philosophers/src/
Dphil_obj_abstract.h4 * SPDX-License-Identifier: Apache-2.0
14 * - a definition for fork_t (a reference to a fork) and fork_obj_t (an
16 * - a 'fork_init' function that initializes the object
17 * - a 'take' function that simulates taking the fork (eg. k_sem_take)
18 * - a 'drop' function that simulates dropping the fork (eg. k_mutex_unlock)
19 * - a 'fork_type_str' string defining the object type
53 #define fork_init(x) k_sem_init(x, 1, 1) argument
55 #define take(x) k_sem_take(x, K_FOREVER) argument
56 #define drop(x) k_sem_give(x) argument
69 #define fork_init(x) k_mutex_init(x) argument
[all …]
/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372.h4 * SPDX-License-Identifier: Apache-2.0
42 #define ADXL372_X_DATA_H 0x08u /* X-axis acceleration data [11:4] */
43 #define ADXL372_X_DATA_L 0x09u /* X-axis acceleration data [3:0] */
44 #define ADXL372_Y_DATA_H 0x0Au /* Y-axis acceleration data [11:4] */
45 #define ADXL372_Y_DATA_L 0x0Bu /* Y-axis acceleration data [3:0] */
46 #define ADXL372_Z_DATA_H 0x0Cu /* Z-axis acceleration data [11:4] */
47 #define ADXL372_Z_DATA_L 0x0Du /* Z-axis acceleration data [3:0] */
48 #define ADXL372_X_MAXPEAK_H 0x15u /* X-axis MaxPeak acceleration data */
49 #define ADXL372_X_MAXPEAK_L 0x16u /* X-axis MaxPeak acceleration data */
50 #define ADXL372_Y_MAXPEAK_H 0x17u /* Y-axis MaxPeak acceleration data */
[all …]
/Zephyr-latest/tests/kernel/common/src/
Dprintk.c4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/sys/printk-hooks.h>
59 "p 112 -10000 -32768 -40000 -22\n"
64 "-42 -42 -42 -42\n"
69 "68719476735 -1 18446744073709551615 ffffffffffffffff\n"
71 "-1 -1 4294967295 ffffffff\n"
75 "0x1 0x 1 0x 1 0x 1\n"
77 "-42 -42 -042 -0000042\n"
82 "68719476735 -1 18446744073709551615 ffffffffffffffff\n"
84 "-1 -1 4294967295 ffffffff\n"
[all …]
/Zephyr-latest/arch/arc/core/
Dfatal.c4 * SPDX-License-Identifier: Apache-2.0
28 ARC_EXCEPTION_DUMP(" r0: 0x%" PRIxPTR " r1: 0x%" PRIxPTR " r2: 0x%" PRIxPTR in dump_arc_esf()
29 " r3: 0x%" PRIxPTR "", esf->r0, esf->r1, esf->r2, esf->r3); in dump_arc_esf()
30 ARC_EXCEPTION_DUMP(" r4: 0x%" PRIxPTR " r5: 0x%" PRIxPTR " r6: 0x%" PRIxPTR in dump_arc_esf()
31 " r7: 0x%" PRIxPTR "", esf->r4, esf->r5, esf->r6, esf->r7); in dump_arc_esf()
32 ARC_EXCEPTION_DUMP(" r8: 0x%" PRIxPTR " r9: 0x%" PRIxPTR " r10: 0x%" PRIxPTR in dump_arc_esf()
33 " r11: 0x%" PRIxPTR "", esf->r8, esf->r9, esf->r10, esf->r11); in dump_arc_esf()
34 ARC_EXCEPTION_DUMP("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR " pc: 0x%" PRIxPTR "", in dump_arc_esf()
35 esf->r12, esf->r13, esf->pc); in dump_arc_esf()
36 ARC_EXCEPTION_DUMP(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", in dump_arc_esf()
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dprci.h4 * SPDX-License-Identifier: Apache-2.0
27 #define PLL_R(x) (((x) & 0x3f) << 0) argument
28 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
29 #define PLL_Q(x) (((x) & 0x7) << 15) argument
30 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
31 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
32 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
33 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
40 #define CORECLKSEL_CORECLKSEL(x) (((x) & 0x1) << 0) argument
/Zephyr-latest/subsys/bluetooth/mesh/
Dsar_cfg_srv.c4 * SPDX-License-Identifier: Apache-2.0
52 LOG_DBG("SAR TX {0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x}", in transmitter_status()
53 tx->seg_int_step, tx->unicast_retrans_count, in transmitter_status()
54 tx->unicast_retrans_without_prog_count, in transmitter_status()
55 tx->unicast_retrans_int_step, tx->unicast_retrans_int_inc, in transmitter_status()
56 tx->multicast_retrans_count, tx->multicast_retrans_int); in transmitter_status()
72 LOG_DBG("SAR RX {0x%02x 0x%02x 0x%02x 0x%02x 0x%02x}", rx->seg_thresh, in receiver_status()
73 rx->ack_delay_inc, rx->discard_timeout, rx->rx_seg_int_step, in receiver_status()
74 rx->ack_retrans_count); in receiver_status()
87 LOG_DBG("src 0x%04x", ctx->addr); in transmitter_get()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dnumaker_m55m1x_clock.h4 * SPDX-License-Identifier: Apache-2.0
275 #define NUMAKER_CLK_SCLKDIV_SCLKDIV(x) (((x) - 1UL) << (0)) argument
276 #define NUMAKER_CLK_HCLKDIV_HCLK2DIV(x) (((x) - 1UL) << (8)) argument
277 #define NUMAKER_CLK_PCLKDIV_PCLK0DIV(x) (((x) - 1UL) << (0)) argument
278 #define NUMAKER_CLK_PCLKDIV_PCLK1DIV(x) (((x) - 1UL) << (4)) argument
279 #define NUMAKER_CLK_PCLKDIV_PCLK2DIV(x) (((x) - 1UL) << (8)) argument
280 #define NUMAKER_CLK_PCLKDIV_PCLK3DIV(x) (((x) - 1UL) << (12)) argument
281 #define NUMAKER_CLK_PCLKDIV_PCLK4DIV(x) (((x) - 1UL) << (16)) argument
282 #define NUMAKER_CLK_STDIV_ST0DIV(x) (((x) - 1UL) << (0)) argument
283 #define NUMAKER_CLK_CANFDDIV_CANFD0DIV(x) (((x) - 1UL) << (0)) argument
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c4 * SPDX-License-Identifier: Apache-2.0
67 "Expected SPI src: PLL1 Q (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected SPI src: PLL2 P (0x%x). Actual: 0x%x", in ZTEST()
75 "Expected SPI src: PLL3 P (0x%x). Actual: 0x%x", in ZTEST()
79 "Expected SPI src: PERCLK (0x%x). Actual: 0x%x", in ZTEST()
92 "Expected PERCK src: HSI_KER (0x%x). Actual: 0x%x", in ZTEST()
96 "Expected PERCK src: CSI_KER (0x%x). Actual: 0x%x", in ZTEST()
100 "Expected PERCK src: HSE (0x%x). Actual: 0x%x", in ZTEST()
103 zassert_true(0, "Unexpected PERCK domain_clk src (0x%x)", in ZTEST()
108 zassert_true(0, "Unexpected domain_clk src(0x%x)", pclken[1].bus); in ZTEST()
[all …]

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