/Zephyr-latest/dts/bindings/mspi/ |
D | snps,designware-ssi.yaml | 2 # SPDX-License-Identifier: Apache-2.0 6 compatible: "snps,designware-ssi" 8 include: [mspi-controller.yaml, pinctrl-device.yaml] 17 aux-reg-enable: 22 fifo-depth: 26 Number of items that can be stored in the TX FIFO. Range: 8-256. 27 If the RX FIFO depth is not specified separately in the rx-fifo-depth 28 property, this value specifies depth of both TX and RX FIFOs. 30 rx-fifo-depth: 33 Number of items that can be stored in the RX FIFO. Range: 8-256. [all …]
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/Zephyr-latest/dts/bindings/spi/ |
D | snps,designware-spi.yaml | 3 # SPDX-License-Identifier: Apache-2.0 7 compatible: "snps,designware-spi" 9 include: [spi-controller.yaml, pinctrl-device.yaml] 18 aux-reg: 24 fifo-depth: 27 RX/TX FIFO depth. Corresponds to the SSI_TX_FIFO_DEPTH 29 Serial Interface. Depth ranges from 2-256. 31 serial-target: 38 max-xfer-size: 45 - 16 [all …]
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D | intel,penwell-spi.yaml | 3 # SPDX-License-Identifier: Apache-2.0 7 compatible: "intel,penwell-spi" 9 include: [spi-controller.yaml, pcie-device.yaml] 15 cs-gpios: 18 pw,cs-mode: 27 pw,cs-output: 37 pw,fifo-depth:
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/Zephyr-latest/dts/bindings/serial/ |
D | altr,jtag-uart.yaml | 3 compatible: "altr,jtag-uart" 5 include: uart-controller.yaml 11 write-fifo-depth: 16 Must be same as Write FIFO: Buffer depth (bytes) in platform designer.
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/Zephyr-latest/dts/bindings/dai/ |
D | nxp,dai-micfil.yaml | 2 # SPDX-License-Identifier: Apache-2.0 6 compatible: "nxp,dai-micfil" 8 include: [base.yaml, pinctrl-device.yaml] 13 dai-index: 21 fifo-depth: 25 Depth (in words) for each channel's FIFO.
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D | nxp,dai-esai.yaml | 2 # SPDX-License-Identifier: Apache-2.0 6 compatible: "nxp,dai-esai" 13 dai-index: 21 tx-fifo-watermark: 29 rx-fifo-watermark: 37 fifo-depth: 40 Use this property to set the FIFO depth that will be reported 44 we mean the actual (hardware) value of the FIFO depth. This is needed 47 Generally, reporting a false FIFO depth should be avoided. Please note 48 that the sanity check for tx/rx-fifo-watermark uses DEFAULT_FIFO_DETPH [all …]
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D | nxp,dai-sai.yaml | 2 # SPDX-License-Identifier: Apache-2.0 11 #include <zephyr/dt-bindings/clock/imx_ccm.h> 14 compatible = "nxp,dai-sai"; 16 interrupt-parent = <&master5>; 19 clock-names = "bus"; 20 dai-index = <1>; 22 dma-names = "tx", "rx"; 23 rx-fifo-watermark = <48>; 24 tx-fifo-watermark = <2>; 25 fifo-depth = <48>; [all …]
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/Zephyr-latest/dts/bindings/i2c/ |
D | cdns,i2c.yaml | 3 # SPDX-License-Identifier: Apache-2.0 14 clock-frequency = <400000>; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 fifo-depth = <8>; 22 include: [i2c-controller.yaml, reset-device.yaml] 35 clock-frequency: 39 fifo-depth:
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/Zephyr-latest/subsys/sip_svc/ |
D | Kconfig | 3 # Copyright (c) 2022-2023, Intel Corporation. 4 # SPDX-License-Identifier: Apache-2.0 11 implementing the platform-specifics via SIP SVC driver. 16 module-str = arm_sip_svc_subsys 40 int "ARM SiP service request message queue depth" 43 Depth of msgq used inside sip_svc controller. 58 int "Delay used for polling asynchronous jobs in micro-seconds"
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/Zephyr-latest/dts/arc/synopsys/ |
D | emsdp.dtsi | 4 * SPDX-License-Identifier: Apache-2.0 9 //#include <zephyr/dt-bindings/i2c/i2c.h> 10 #include <zephyr/dt-bindings/gpio/gpio.h> 16 #address-cells = <1>; 17 #size-cells = <0>; 26 intc: arcv2-intc { 27 compatible = "snps,arcv2-intc"; 28 interrupt-controller; 29 #interrupt-cells = <2>; 33 compatible = "snps,arc-timer"; [all …]
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D | arc_hs4xd.dtsi | 4 * SPDX-License-Identifier: Apache-2.0 9 #include <zephyr/dt-bindings/i2c/i2c.h> 10 #include <zephyr/dt-bindings/gpio/gpio.h> 14 #address-cells = <1>; 15 #size-cells = <0>; 43 intc: arcv2-intc { 44 compatible = "snps,arcv2-intc"; 45 interrupt-controller; 46 #interrupt-cells = <2>; 50 idu_intc: idu-interrupt-controller { [all …]
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D | arc_hsdk.dtsi | 4 * SPDX-License-Identifier: Apache-2.0 9 #include <zephyr/dt-bindings/i2c/i2c.h> 10 #include <zephyr/dt-bindings/gpio/gpio.h> 14 #address-cells = <1>; 15 #size-cells = <0>; 43 intc: arcv2-intc { 44 compatible = "snps,arcv2-intc"; 45 interrupt-controller; 46 #interrupt-cells = <2>; 50 idu_intc: idu-interrupt-controller { [all …]
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/Zephyr-latest/arch/xtensa/include/ |
D | xtensa_backtrace.h | 4 * SPDX-License-Identifier: Apache-2.0 47 * (B -> A -> X -> esp_backtrace_get_start), 49 * - Flush CPU registers and window frames onto the current stack 50 * - Return PC and SP of function A (i.e. start of the stack's backtrace) 51 * - Return PC of function B (i.e. next_pc) 69 * stack frame(i-1) on the same call stack (i.e. the caller of frame(i)). 74 * - Frame structure updated with SP and PC of frame(i-1). 75 * next_pc now points to frame(i-2). 76 * - If a next_pc of 0 is returned, it indicates that frame(i-1) 82 * - True if the SP and PC of the next frame(i-1) are sane [all …]
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/Zephyr-latest/dts/bindings/i2s/ |
D | litex,i2s.yaml | 4 # SPDX-License-Identifier: Apache-2.0 10 include: i2s-controller.yaml 16 fifo-depth:
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/Zephyr-latest/arch/x86/core/ |
D | Kconfig.intel64 | 1 # Intel64-specific X86 subarchitecture options 4 # SPDX-License-Identifier: Apache-2.0 29 support limited call-tree depth and must fit into the low core, 61 int "Maximum IRQ nesting depth" 91 supporting user-level threads that are protected from each other and
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/Zephyr-latest/scripts/ci/ |
D | twister_report_analyzer.py | 3 # SPDX-License-Identifier: Apache-2.0 17 def create_parser() -> argparse.ArgumentParser: 26 > python %(prog)s twister_reports/*.json --long-summary 27 … The summary will be saved to twister_report_summary.json file unless --output option is used. 28 …To save error summary to CSV file, use --output-csv option (number of test files is limited to 100… 29 > python %(prog)s twister_reports/*.json --output-csv twister_report_summary.csv 30 One can use --error-patterns option to provide custom error patterns file: 31 > python %(prog)s **/twister.json --error-patterns error_patterns.txt 37 '--error-patterns', 42 '--output', [all …]
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/Zephyr-latest/samples/modules/lvgl/demos/boards/ |
D | mimxrt595_evk_mimxrt595s_cm33.conf | 4 # SPDX-License-Identifier: Apache-2.0 7 # Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a 8 # 1280x720 display in a 16-bpp format (e.g. RGB565), this is (1280 / 8) * (720 / 4) * 2 = 57600
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/Zephyr-latest/samples/drivers/display/boards/ |
D | mimxrt1170_evk_mimxrt1176_cm7_A.conf | 4 # SPDX-License-Identifier: Apache-2.0 7 # Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a 8 # 1280x720 display in a 32-bpp format (e.g. ARGB8888), this is (720 / 8) * (720 / 4) * 4 = 64800
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D | mimxrt595_evk_mimxrt595s_cm33.conf | 4 # SPDX-License-Identifier: Apache-2.0 7 # Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a 8 # 1280x720 display in a 32-bpp format (e.g. ARGB8888), this is (720 / 8) * (720 / 4) * 4 = 64800
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D | mimxrt1170_evkb_cm7.conf | 4 # SPDX-License-Identifier: Apache-2.0 7 # Sample will allocate buffer equal to: (panelwidth / 8) * (panelwidth / 4) * pixel depth. For a 8 # 1280x720 display in a 32-bpp format (e.g. ARGB8888), this is (720 / 8) * (720 / 4) * 4 = 64800
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/Zephyr-latest/.github/workflows/ |
D | compliance.yml | 6 - edited 7 - opened 8 - reopened 9 - synchronize 13 runs-on: ubuntu-22.04 16 - name: Update PATH for west 20 - name: Checkout the code 24 fetch-depth: 0 26 - name: Rebase onto the target branch 30 git config --global user.email "you@example.com" [all …]
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/Zephyr-latest/drivers/dai/intel/ssp/ |
D | ssp.h | 4 * SPDX-License-Identifier: Apache-2.0 30 #include "dai-params-intel-ipc3.h" 31 #include "dai-params-intel-ipc4.h" 34 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo)) 37 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo)) 45 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1) 48 /* the SSP port fifo depth */ 51 /* the watermark for the SSP fifo depth setting */ 79 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly. 123 uint32_t depth; member
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/Zephyr-latest/arch/xtensa/core/ |
D | xtensa_backtrace.c | 4 * SPDX-License-Identifier: Apache-2.0 38 return pc - 3; in xtensa_cpu_process_stack_pc() 82 if (xtensa_is_outside_stack_bounds((uintptr_t)frame->sp, 0, UINT32_MAX)) { in xtensa_backtrace_get_next_frame() 86 /* Use frame(i-1)'s BS area located below frame(i)'s in xtensa_backtrace_get_next_frame() 87 * sp to get frame(i-1)'s sp and frame(i-2)'s pc in xtensa_backtrace_get_next_frame() 91 char *base_save = (char *)frame->sp; in xtensa_backtrace_get_next_frame() 93 frame->pc = frame->next_pc; in xtensa_backtrace_get_next_frame() 94 /* If next_pc = 0, indicates frame(i-1) is the last in xtensa_backtrace_get_next_frame() 97 frame->next_pc = *((uint32_t *)(base_save - 16)); in xtensa_backtrace_get_next_frame() 98 frame->sp = *((uint32_t *)(base_save - 12)); in xtensa_backtrace_get_next_frame() [all …]
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/Zephyr-latest/doc/connectivity/networking/api/ |
D | trickle.rst | 8 :depth: 2 17 low-power and lossy networks) to exchange information in a highly
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D | lldp.rst | 8 :depth: 2 13 The Link Layer Discovery Protocol (LLDP) is a vendor-neutral link layer
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