1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/adc/adc.h>
7#include <zephyr/dt-bindings/i2c/i2c.h>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9
10/ {
11	clocks {
12		uartclk: apb-pclk {
13			compatible = "fixed-clock";
14			clock-frequency = <DT_FREQ_M(24)>;
15			#clock-cells = <0>;
16		};
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			compatible = "arm,cortex-m4f";
25			reg = <0>;
26			cpu-power-states = <&idle &suspend_to_ram>;
27			#address-cells = <1>;
28			#size-cells = <1>;
29
30			itm: itm@e0000000 {
31				compatible = "arm,armv7m-itm";
32				reg = <0xe0000000 0x1000>;
33				swo-ref-frequency = <DT_FREQ_M(6)>;
34			};
35		};
36
37		power-states {
38			idle: idle {
39				compatible = "zephyr,power-state";
40				power-state-name = "suspend-to-idle";
41				/* As Apollo3blueplus datasheet, run_to_sleep and sleep_to_run
42				 * transition time are both lower than 1us, but considering
43				 * the software overhead we set a bigger value.
44				 */
45				min-residency-us = <100>;
46				exit-latency-us = <5>;
47			};
48
49			suspend_to_ram: suspend_to_ram {
50				compatible = "zephyr,power-state";
51				power-state-name = "suspend-to-ram";
52				/* As Apollo3blueplus datasheet, run_to_deepsleep transition time
53				 * is the software overhead 1us and deepsleep_to_run transition
54				 * time is about 25us,but considering the software overhead,
55				 * we set a bigger value.
56				 */
57				min-residency-us = <2000>;
58				exit-latency-us = <125>;
59			};
60		};
61	};
62
63	/* TCM */
64	tcm: tcm@10000000 {
65		compatible = "zephyr,memory-region";
66		reg = <0x10000000 0x10000>;
67		zephyr,memory-region = "ITCM";
68	};
69
70	/* SRAM */
71	sram0: memory@10010000 {
72		compatible = "mmio-sram";
73		reg = <0x10010000 0xB0000>;
74	};
75
76	xip0: memory@52000000 {
77		compatible = "zephyr,memory-region";
78		reg = <0x52000000 0x2000000>;
79		zephyr,memory-region = "XIP0";
80	};
81
82	xip1: memory@54000000 {
83		compatible = "zephyr,memory-region";
84		reg = <0x54000000 0x2000000>;
85		zephyr,memory-region = "XIP1";
86	};
87
88	xip2: memory@56000000 {
89		compatible = "zephyr,memory-region";
90		reg = <0x56000000 0x2000000>;
91		zephyr,memory-region = "XIP2";
92	};
93
94	soc {
95		compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
96
97		flash: flash-controller@c000 {
98			compatible = "ambiq,flash-controller";
99			reg = <0x0000c000 0x1f4000>;
100
101			#address-cells = <1>;
102			#size-cells = <1>;
103
104			/* Flash region */
105			flash0: flash@c000 {
106				compatible = "soc-nv-flash";
107				reg = <0x0000c000 0x1f4000>;
108			};
109		};
110
111		pwrcfg: pwrcfg@40021000 {
112			compatible = "ambiq,pwrctrl";
113			reg = <0x40021000 0x400>;
114			#pwrcfg-cells = <2>;
115		};
116
117		stimer0: stimer@40008140 {
118			compatible = "ambiq,stimer";
119			reg = <0x40008140 0x80>;
120			interrupts = <23 0>;
121			status = "okay";
122		};
123
124		counter0: counter@40008000 {
125			compatible = "ambiq,counter";
126			reg = <0x40008000 0x20>;
127			interrupts = <14 0>;
128			clock-frequency = <DT_FREQ_M(3)>;
129			clk-source = <2>;
130			status = "disabled";
131		};
132
133		counter1: counter@40008020 {
134			compatible = "ambiq,counter";
135			reg = <0x40008020 0x20>;
136			interrupts = <14 0>;
137			clock-frequency = <DT_FREQ_M(3)>;
138			clk-source = <2>;
139			status = "disabled";
140		};
141
142		counter2: counter@40008040 {
143			compatible = "ambiq,counter";
144			reg = <0x40008040 0x20>;
145			interrupts = <14 0>;
146			clock-frequency = <DT_FREQ_M(3)>;
147			clk-source = <2>;
148			status = "disabled";
149		};
150
151		counter3: counter@40008060 {
152			compatible = "ambiq,counter";
153			reg = <0x40008060 0x20>;
154			interrupts = <14 0>;
155			clock-frequency = <DT_FREQ_M(3)>;
156			clk-source = <2>;
157			status = "disabled";
158		};
159
160		counter4: counter@40008080 {
161			compatible = "ambiq,counter";
162			reg = <0x40008080 0x20>;
163			interrupts = <14 0>;
164			clock-frequency = <DT_FREQ_M(3)>;
165			clk-source = <2>;
166			status = "disabled";
167		};
168
169		counter5: counter@400080a0 {
170			compatible = "ambiq,counter";
171			reg = <0x400080A0 0x20>;
172			interrupts = <14 0>;
173			clock-frequency = <DT_FREQ_M(3)>;
174			clk-source = <2>;
175			status = "disabled";
176		};
177
178		counter6: counter@400080c0 {
179			compatible = "ambiq,counter";
180			reg = <0x400080C0 0x20>;
181			interrupts = <14 0>;
182			clock-frequency = <DT_FREQ_M(3)>;
183			clk-source = <2>;
184			status = "disabled";
185		};
186
187		counter7: counter@400080e0 {
188			compatible = "ambiq,counter";
189			reg = <0x400080E0 0x20>;
190			interrupts = <14 0>;
191			clock-frequency = <DT_FREQ_M(3)>;
192			clk-source = <2>;
193			status = "disabled";
194		};
195
196		uart0: uart@4001c000 {
197			compatible = "ambiq,uart", "arm,pl011";
198			reg = <0x4001c000 0x1000>;
199			interrupts = <15 0>;
200			interrupt-names = "UART0";
201			status = "disabled";
202			clocks = <&uartclk>;
203			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
204			zephyr,pm-device-runtime-auto;
205		};
206
207		uart1: uart@4001d000 {
208			compatible = "ambiq,uart", "arm,pl011";
209			reg = <0x4001d000 0x1000>;
210			interrupts = <16 0>;
211			interrupt-names = "UART1";
212			status = "disabled";
213			clocks = <&uartclk>;
214			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
215			zephyr,pm-device-runtime-auto;
216		};
217
218		spid0: spi@50000100 {
219			compatible = "ambiq,spid";
220			reg = <0x50000100 0x1000>;
221			#address-cells = <1>;
222			#size-cells = <0>;
223			interrupts = <4 0>;
224			status = "disabled";
225			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
226			zephyr,pm-device-runtime-auto;
227		};
228
229		spi0: spi@50004000 {
230			compatible = "ambiq,spi";
231			reg = <0x50004000 0x1000>;
232			#address-cells = <1>;
233			#size-cells = <0>;
234			interrupts = <6 0>;
235			status = "disabled";
236			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
237			zephyr,pm-device-runtime-auto;
238		};
239
240		spi1: spi@50005000 {
241			compatible = "ambiq,spi";
242			reg = <0x50005000 0x1000>;
243			#address-cells = <1>;
244			#size-cells = <0>;
245			interrupts = <7 0>;
246			status = "disabled";
247			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
248			zephyr,pm-device-runtime-auto;
249		};
250
251		spi2: spi@50006000 {
252			compatible = "ambiq,spi";
253			reg = <0x50006000 0x1000>;
254			#address-cells = <1>;
255			#size-cells = <0>;
256			interrupts = <8 0>;
257			status = "disabled";
258			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
259			zephyr,pm-device-runtime-auto;
260		};
261
262		spi3: spi@50007000 {
263			compatible = "ambiq,spi";
264			reg = <0x50007000 0x1000>;
265			#address-cells = <1>;
266			#size-cells = <0>;
267			interrupts = <9 0>;
268			status = "disabled";
269			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
270			zephyr,pm-device-runtime-auto;
271		};
272
273		spi4: spi@50008000 {
274			compatible = "ambiq,spi";
275			reg = <0x50008000 0x1000>;
276			#address-cells = <1>;
277			#size-cells = <0>;
278			interrupts = <10 0>;
279			status = "disabled";
280			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
281			zephyr,pm-device-runtime-auto;
282		};
283
284		spi5: spi@50009000 {
285			compatible = "ambiq,spi";
286			reg = <0x50009000 0x1000>;
287			#address-cells = <1>;
288			#size-cells = <0>;
289			interrupts = <11 0>;
290			status = "disabled";
291			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
292			zephyr,pm-device-runtime-auto;
293		};
294
295		i2c0: i2c@50004000 {
296			compatible = "ambiq,i2c";
297			reg = <0x50004000 0x1000>;
298			#address-cells = <1>;
299			#size-cells = <0>;
300			interrupts = <6 0>;
301			status = "disabled";
302			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
303			zephyr,pm-device-runtime-auto;
304		};
305
306		i2c1: i2c@50005000 {
307			compatible = "ambiq,i2c";
308			reg = <0x50005000 0x1000>;
309			#address-cells = <1>;
310			#size-cells = <0>;
311			interrupts = <7 0>;
312			status = "disabled";
313			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
314			zephyr,pm-device-runtime-auto;
315		};
316
317		i2c2: i2c@50006000 {
318			compatible = "ambiq,i2c";
319			reg = <0x50006000 0x1000>;
320			#address-cells = <1>;
321			#size-cells = <0>;
322			interrupts = <8 0>;
323			status = "disabled";
324			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
325			zephyr,pm-device-runtime-auto;
326		};
327
328		i2c3: i2c@50007000 {
329			compatible = "ambiq,i2c";
330			reg = <0x50007000 0x1000>;
331			#address-cells = <1>;
332			#size-cells = <0>;
333			interrupts = <9 0>;
334			status = "disabled";
335			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
336			zephyr,pm-device-runtime-auto;
337		};
338
339		i2c4: i2c@50008000 {
340			compatible = "ambiq,i2c";
341			reg = <0x50008000 0x1000>;
342			#address-cells = <1>;
343			#size-cells = <0>;
344			interrupts = <10 0>;
345			status = "disabled";
346			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
347			zephyr,pm-device-runtime-auto;
348		};
349
350		i2c5: i2c@50009000 {
351			compatible = "ambiq,i2c";
352			reg = <0x50009000 0x1000>;
353			#address-cells = <1>;
354			#size-cells = <0>;
355			interrupts = <11 0>;
356			status = "disabled";
357			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
358			zephyr,pm-device-runtime-auto;
359		};
360
361		adc0: adc@50010000 {
362			compatible = "ambiq,adc";
363			reg = <0x50010000 0x400>;
364			interrupts = <18 0>;
365			interrupt-names = "ADC";
366			channel-count = <10>;
367			internal-vref-mv = <1500>;
368			status = "disabled";
369			#io-channel-cells = <1>;
370			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
371		};
372
373		mspi0: mspi@50014000 {
374			compatible = "ambiq,mspi-controller";
375			reg = <0x50014000 0x400>,<0x52000000 0x2000000>;
376			clock-frequency = <48000000>;
377			interrupts = <20 0>;
378			#address-cells = <1>;
379			#size-cells = <0>;
380			status = "disabled";
381			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
382		};
383
384		mspi1: mspi@50015000 {
385			compatible = "ambiq,mspi-controller";
386			reg = <0x50015000 0x400>,<0x54000000 0x2000000>;
387			clock-frequency = <48000000>;
388			interrupts = <32 0>;
389			#address-cells = <1>;
390			#size-cells = <0>;
391			status = "disabled";
392			ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
393		};
394
395		mspi2: mspi@50016000 {
396			compatible = "ambiq,mspi-controller";
397			clock-frequency = <48000000>;
398			reg = <0x50016000 0x400>,<0x56000000 0x2000000>;
399			interrupts = <33 0>;
400			#address-cells = <1>;
401			#size-cells = <0>;
402			status = "disabled";
403			ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
404		};
405
406		rtc0: rtc@40004240 {
407			compatible = "ambiq,rtc";
408			reg = <0x40004240 0xD0>;
409			interrupts = <2 0>;
410			alarms-count = <1>;
411			status = "disabled";
412		};
413
414		bleif: spi@5000c000 {
415			compatible = "ambiq,spi-bleif";
416			reg = <0x5000c000 0x414>;
417			interrupts = <12 1>;
418			#address-cells = <1>;
419			#size-cells = <0>;
420			status = "disabled";
421			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
422
423			bt_hci_apollo: bt-hci@0 {
424				compatible = "ambiq,bt-hci-spi";
425				spi-max-frequency = <DT_FREQ_M(6)>;
426				reg = <0>;
427			};
428		};
429
430		pinctrl: pin-controller@40010000 {
431			compatible = "ambiq,apollo3-pinctrl";
432			reg = <0x40010000 0x800>;
433			#address-cells = <1>;
434			#size-cells = <0>;
435
436			gpio: gpio@40010000 {
437				compatible = "ambiq,gpio";
438				gpio-map-mask = <0xffffffe0 0xffffffc0>;
439				gpio-map-pass-thru = <0x1f 0x3f>;
440				gpio-map = <
441					0x00 0x0 &gpio0_31 0x0 0x0
442					0x20 0x0 &gpio32_63 0x0 0x0
443					0x40 0x0 &gpio64_95 0x0 0x0
444				>;
445				reg = <0x40010000>;
446				#gpio-cells = <2>;
447				#address-cells = <1>;
448				#size-cells = <0>;
449				ranges;
450
451				gpio0_31: gpio0_31@0 {
452					compatible = "ambiq,gpio-bank";
453					gpio-controller;
454					#gpio-cells = <2>;
455					reg = <0>;
456					interrupts = <13 0>;
457					status = "disabled";
458				};
459
460				gpio32_63: gpio32_63@20 {
461					compatible = "ambiq,gpio-bank";
462					gpio-controller;
463					#gpio-cells = <2>;
464					reg = <0x20>;
465					interrupts = <13 0>;
466					status = "disabled";
467				};
468
469				gpio64_95: gpio64_95@40 {
470					compatible = "ambiq,gpio-bank";
471					gpio-controller;
472					#gpio-cells = <2>;
473					reg = <0x40>;
474					interrupts = <13 0>;
475					status = "disabled";
476					ngpios = <10>;
477				};
478			};
479		};
480
481		wdt0: watchdog@40024000 {
482			compatible = "ambiq,watchdog";
483			reg = <0x40024000 0x400>;
484			interrupts = <1 0>;
485			clock-frequency = <16>;
486			status = "disabled";
487		};
488	};
489};
490
491&nvic {
492	arm,num-irq-priority-bits = <3>;
493};
494