1/* 2 * Copyright (c) 2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <nordic/nrf_common.dtsi> 9 10#include <zephyr/dt-bindings/adc/nrf-saadc.h> 11#include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h> 12#include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h> 13#include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h> 14#include <zephyr/dt-bindings/misc/nordic-tddconf.h> 15#include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h> 16#include <zephyr/dt-bindings/power/nordic-nrf-gpd.h> 17 18/delete-node/ &sw_pwm; 19 20/ { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpuapp: cpu@2 { 29 compatible = "arm,cortex-m33"; 30 reg = <2>; 31 device_type = "cpu"; 32 clocks = <&cpuapp_hsfll>; 33 clock-frequency = <DT_FREQ_M(320)>; 34 cpu-power-states = <&idle_cache_disabled &s2ram>; 35 }; 36 37 cpurad: cpu@3 { 38 compatible = "arm,cortex-m33"; 39 reg = <3>; 40 device_type = "cpu"; 41 clocks = <&cpurad_hsfll>; 42 clock-frequency = <DT_FREQ_M(256)>; 43 cpu-power-states = <&idle_cache_disabled>; 44 }; 45 46 cpuppr: cpu@d { 47 compatible = "nordic,vpr"; 48 reg = <13>; 49 device_type = "cpu"; 50 clocks = <&fll16m>; 51 clock-frequency = <DT_FREQ_M(16)>; 52 riscv,isa = "rv32emc"; 53 nordic,bus-width = <32>; 54 55 cpuppr_vevif_rx: mailbox { 56 compatible = "nordic,nrf-vevif-task-rx"; 57 status = "disabled"; 58 interrupt-parent = <&cpuppr_clic>; 59 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, 60 <1 NRF_DEFAULT_IRQ_PRIORITY>, 61 <2 NRF_DEFAULT_IRQ_PRIORITY>, 62 <3 NRF_DEFAULT_IRQ_PRIORITY>, 63 <4 NRF_DEFAULT_IRQ_PRIORITY>, 64 <5 NRF_DEFAULT_IRQ_PRIORITY>, 65 <6 NRF_DEFAULT_IRQ_PRIORITY>, 66 <7 NRF_DEFAULT_IRQ_PRIORITY>, 67 <8 NRF_DEFAULT_IRQ_PRIORITY>, 68 <9 NRF_DEFAULT_IRQ_PRIORITY>, 69 <10 NRF_DEFAULT_IRQ_PRIORITY>, 70 <11 NRF_DEFAULT_IRQ_PRIORITY>, 71 <12 NRF_DEFAULT_IRQ_PRIORITY>, 72 <13 NRF_DEFAULT_IRQ_PRIORITY>, 73 <14 NRF_DEFAULT_IRQ_PRIORITY>, 74 <15 NRF_DEFAULT_IRQ_PRIORITY>; 75 #mbox-cells = <1>; 76 nordic,tasks = <16>; 77 nordic,tasks-mask = <0xfffffff0>; 78 }; 79 }; 80 81 cpuflpr: cpu@e { 82 compatible = "nordic,vpr"; 83 reg = <14>; 84 device_type = "cpu"; 85 clock-frequency = <DT_FREQ_M(320)>; 86 riscv,isa = "rv32emc"; 87 nordic,bus-width = <32>; 88 89 cpuflpr_vevif_rx: mailbox { 90 compatible = "nordic,nrf-vevif-task-rx"; 91 status = "disabled"; 92 interrupt-parent = <&cpuflpr_clic>; 93 interrupts = <0 NRF_DEFAULT_IRQ_PRIORITY>, 94 <1 NRF_DEFAULT_IRQ_PRIORITY>, 95 <2 NRF_DEFAULT_IRQ_PRIORITY>, 96 <3 NRF_DEFAULT_IRQ_PRIORITY>, 97 <4 NRF_DEFAULT_IRQ_PRIORITY>, 98 <5 NRF_DEFAULT_IRQ_PRIORITY>, 99 <6 NRF_DEFAULT_IRQ_PRIORITY>, 100 <7 NRF_DEFAULT_IRQ_PRIORITY>, 101 <8 NRF_DEFAULT_IRQ_PRIORITY>, 102 <9 NRF_DEFAULT_IRQ_PRIORITY>, 103 <10 NRF_DEFAULT_IRQ_PRIORITY>, 104 <11 NRF_DEFAULT_IRQ_PRIORITY>, 105 <12 NRF_DEFAULT_IRQ_PRIORITY>, 106 <13 NRF_DEFAULT_IRQ_PRIORITY>, 107 <14 NRF_DEFAULT_IRQ_PRIORITY>, 108 <15 NRF_DEFAULT_IRQ_PRIORITY>, 109 <16 NRF_DEFAULT_IRQ_PRIORITY>, 110 <17 NRF_DEFAULT_IRQ_PRIORITY>, 111 <18 NRF_DEFAULT_IRQ_PRIORITY>, 112 <19 NRF_DEFAULT_IRQ_PRIORITY>, 113 <20 NRF_DEFAULT_IRQ_PRIORITY>, 114 <21 NRF_DEFAULT_IRQ_PRIORITY>, 115 <22 NRF_DEFAULT_IRQ_PRIORITY>, 116 <23 NRF_DEFAULT_IRQ_PRIORITY>, 117 <24 NRF_DEFAULT_IRQ_PRIORITY>, 118 <25 NRF_DEFAULT_IRQ_PRIORITY>, 119 <26 NRF_DEFAULT_IRQ_PRIORITY>, 120 <27 NRF_DEFAULT_IRQ_PRIORITY>, 121 <28 NRF_DEFAULT_IRQ_PRIORITY>, 122 <29 NRF_DEFAULT_IRQ_PRIORITY>, 123 <30 NRF_DEFAULT_IRQ_PRIORITY>, 124 <31 NRF_DEFAULT_IRQ_PRIORITY>; 125 #mbox-cells = <1>; 126 nordic,tasks = <32>; 127 nordic,tasks-mask = <0xffff0000>; 128 }; 129 }; 130 131 power-states { 132 // substate-id = <0>; is reserved for "idle", cache powered on 133 // substate-id = <1>; is reserved for "idle-cache-retained" 134 idle_cache_disabled: idle_cache_disabled { 135 compatible = "zephyr,power-state"; 136 power-state-name = "suspend-to-idle"; 137 substate-id = <2>; 138 min-residency-us = <1000>; 139 exit-latency-us = <30>; 140 }; 141 s2ram: s2ram { 142 compatible = "zephyr,power-state"; 143 power-state-name = "suspend-to-ram"; 144 min-residency-us = <2000>; 145 exit-latency-us = <260>; 146 }; 147 }; 148 }; 149 150 reserved-memory { 151 #address-cells = <1>; 152 #size-cells = <1>; 153 154 suit_storage_partition: memory@e1ed000 { 155 reg = <0xe1ed000 DT_SIZE_K(20)>; 156 }; 157 }; 158 159 clocks { 160 hfxo: hfxo { 161 compatible = "nordic,nrf54h-hfxo"; 162 status = "disabled"; 163 #clock-cells = <0>; 164 clock-frequency = <DT_FREQ_M(32)>; 165 }; 166 167 lfxo: lfxo { 168 compatible = "nordic,nrf54h-lfxo"; 169 status = "disabled"; 170 #clock-cells = <0>; 171 clock-frequency = <32768>; 172 }; 173 174 fll16m: fll16m { 175 compatible = "nordic,nrf-fll16m"; 176 #clock-cells = <0>; 177 clock-frequency = <DT_FREQ_M(16)>; 178 open-loop-accuracy-ppm = <20000>; 179 closed-loop-base-accuracy-ppm = <5000>; 180 clocks = <&hfxo>, <&lfxo>; 181 clock-names = "hfxo", "lfxo"; 182 }; 183 184 hsfll120: hsfll120 { 185 compatible = "nordic,nrf-hsfll-global"; 186 clocks = <&fll16m>; 187 #clock-cells = <0>; 188 clock-frequency = <320000000>; 189 supported-clock-frequencies = <64000000 190 128000000 191 256000000 192 320000000>; 193 }; 194 195 lfclk: lfclk { 196 compatible = "nordic,nrf-lfclk"; 197 #clock-cells = <0>; 198 clock-frequency = <32768>; 199 status = "okay"; 200 lfrc-accuracy-ppm = <500>; 201 lflprc-accuracy-ppm = <1000>; 202 clocks = <&hfxo>, <&lfxo>; 203 clock-names = "hfxo", "lfxo"; 204 }; 205 }; 206 207 gpd: global-power-domain { 208 compatible = "nordic,nrf-gpd"; 209 #power-domain-cells = <1>; 210 }; 211 212 soc { 213 #address-cells = <1>; 214 #size-cells = <1>; 215 216 mram1x: mram@e000000 { 217 compatible = "nordic,mram"; 218 reg = <0xe000000 DT_SIZE_K(2048)>; 219 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 220 erase-block-size = <4096>; 221 write-block-size = <16>; 222 }; 223 224 cpuapp_uicr: uicr@fff8000 { 225 compatible = "nordic,nrf-uicr-v2"; 226 reg = <0xfff8000 DT_SIZE_K(2)>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 ranges = <0x0 0xfff8000 DT_SIZE_K(2)>; 230 domain = <2>; 231 232 bicr: bicr@7b0 { 233 compatible = "nordic,nrf-bicr"; 234 reg = <0x7b0 48>; 235 }; 236 }; 237 238 cpurad_uicr: uicr@fffa000 { 239 compatible = "nordic,nrf-uicr-v2"; 240 reg = <0xfffa000 DT_SIZE_K(2)>; 241 domain = <3>; 242 }; 243 244 ficr: ficr@fffe000 { 245 compatible = "nordic,nrf-ficr"; 246 reg = <0xfffe000 DT_SIZE_K(2)>; 247 #nordic,ficr-cells = <1>; 248 }; 249 250 cpuapp_ram0: sram@22000000 { 251 compatible = "mmio-sram"; 252 reg = <0x22000000 DT_SIZE_K(32)>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0x0 0x22000000 0x8000>; 256 }; 257 258 cpurad_ram0: sram@23000000 { 259 compatible = "mmio-sram"; 260 reg = <0x23000000 DT_SIZE_K(192)>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0x0 0x23000000 0x30000>; 264 }; 265 266 cpuapp_peripherals: peripheral@52000000 { 267 #address-cells = <1>; 268 #size-cells = <1>; 269 reg = <0x52000000 0x1000000>; 270 ranges = <0x0 0x52000000 0x1000000>; 271 272 cpuapp_hsfll: clock@d000 { 273 compatible = "nordic,nrf-hsfll-local"; 274 #clock-cells = <0>; 275 reg = <0xd000 0x1000>; 276 clocks = <&fll16m>; 277 clock-frequency = <DT_FREQ_M(320)>; 278 nordic,ficrs = 279 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, 280 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, 281 <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; 282 nordic,ficr-names = "vsup", "coarse", "fine"; 283 }; 284 285 cpuapp_ipct: ipct@13000 { 286 compatible = "nordic,nrf-ipct-local"; 287 reg = <0x13000 0x1000>; 288 status = "disabled"; 289 channels = <4>; 290 interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, 291 <65 NRF_DEFAULT_IRQ_PRIORITY>; 292 }; 293 294 cpuapp_wdt010: watchdog@14000 { 295 compatible = "nordic,nrf-wdt"; 296 reg = <0x14000 0x1000>; 297 status = "disabled"; 298 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 299 clocks = <&lfclk>; 300 }; 301 302 cpuapp_wdt011: watchdog@15000 { 303 compatible = "nordic,nrf-wdt"; 304 reg = <0x15000 0x1000>; 305 status = "disabled"; 306 interrupts = <21 NRF_DEFAULT_IRQ_PRIORITY>; 307 clocks = <&lfclk>; 308 }; 309 310 cpuapp_resetinfo: resetinfo@1e000 { 311 compatible = "nordic,nrf-resetinfo"; 312 reg = <0x1e000 0x1000>; 313 }; 314 315 cpuapp_ieee802154: ieee802154 { 316 compatible = "nordic,nrf-ieee802154"; 317 status = "disabled"; 318 }; 319 }; 320 321 cpurad_peripherals: peripheral@53000000 { 322 #address-cells = <1>; 323 #size-cells = <1>; 324 ranges = <0x0 0x53000000 0x1000000>; 325 326 cpurad_hsfll: clock@d000 { 327 compatible = "nordic,nrf-hsfll-local"; 328 #clock-cells = <0>; 329 reg = <0xd000 0x1000>; 330 clocks = <&fll16m>; 331 clock-frequency = <DT_FREQ_M(256)>; 332 nordic,ficrs = 333 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, 334 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, 335 <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; 336 nordic,ficr-names = "vsup", "coarse", "fine"; 337 }; 338 339 cpurad_wdt010: watchdog@13000 { 340 compatible = "nordic,nrf-wdt"; 341 reg = <0x13000 0x1000>; 342 status = "disabled"; 343 interrupts = <19 NRF_DEFAULT_IRQ_PRIORITY>; 344 clocks = <&lfclk>; 345 }; 346 347 cpurad_wdt011: watchdog@14000 { 348 compatible = "nordic,nrf-wdt"; 349 reg = <0x14000 0x1000>; 350 status = "disabled"; 351 interrupts = <20 NRF_DEFAULT_IRQ_PRIORITY>; 352 clocks = <&lfclk>; 353 }; 354 355 cpurad_resetinfo: resetinfo@1e000 { 356 compatible = "nordic,nrf-resetinfo"; 357 reg = <0x1e000 0x1000>; 358 }; 359 360 dppic020: dppic@22000 { 361 compatible = "nordic,nrf-dppic-local"; 362 reg = <0x22000 0x1000>; 363 status = "disabled"; 364 }; 365 366 cpurad_ipct: ipct@24000 { 367 compatible = "nordic,nrf-ipct-local"; 368 reg = <0x24000 0x1000>; 369 status = "disabled"; 370 channels = <8>; 371 interrupts = <64 NRF_DEFAULT_IRQ_PRIORITY>, 372 <65 NRF_DEFAULT_IRQ_PRIORITY>; 373 }; 374 375 egu020: egu@25000 { 376 compatible = "nordic,nrf-egu"; 377 reg = <0x25000 0x1000>; 378 status = "disabled"; 379 interrupts = <37 NRF_DEFAULT_IRQ_PRIORITY>; 380 }; 381 382 timer020: timer@28000 { 383 compatible = "nordic,nrf-timer"; 384 reg = <0x28000 0x1000>; 385 status = "disabled"; 386 cc-num = <8>; 387 interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>; 388 clocks = <&hfxo>; 389 max-bit-width = <32>; 390 prescaler = <0>; 391 }; 392 393 timer021: timer@29000 { 394 compatible = "nordic,nrf-timer"; 395 reg = <0x29000 0x1000>; 396 status = "disabled"; 397 cc-num = <8>; 398 interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>; 399 clocks = <&hfxo>; 400 max-bit-width = <32>; 401 prescaler = <0>; 402 }; 403 404 timer022: timer@2a000 { 405 compatible = "nordic,nrf-timer"; 406 reg = <0x2a000 0x1000>; 407 status = "disabled"; 408 cc-num = <8>; 409 interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>; 410 clocks = <&hfxo>; 411 max-bit-width = <32>; 412 prescaler = <0>; 413 }; 414 415 rtc: rtc@2b000 { 416 compatible = "nordic,nrf-rtc"; 417 reg = <0x2b000 0x1000>; 418 status = "disabled"; 419 cc-num = <4>; 420 clock-frequency = <32768>; 421 interrupts = <43 NRF_DEFAULT_IRQ_PRIORITY>; 422 clocks = <&lfclk>; 423 prescaler = <1>; 424 }; 425 426 radio: radio@2c000 { 427 compatible = "nordic,nrf-radio"; 428 reg = <0x2c000 0x1000>; 429 status = "disabled"; 430 ble-2mbps-supported; 431 ble-coded-phy-supported; 432 cs-supported; 433 dfe-supported; 434 ieee802154-supported; 435 interrupts = <44 NRF_DEFAULT_IRQ_PRIORITY>; 436 clocks = <&hfxo>; 437 438 cpurad_ieee802154: ieee802154 { 439 compatible = "nordic,nrf-ieee802154"; 440 status = "disabled"; 441 }; 442 }; 443 444 ccm030: ccm@3a000 { 445 compatible = "nordic,nrf-ccm"; 446 reg = <0x3a000 0x1000>; 447 interrupts = <58 NRF_DEFAULT_IRQ_PRIORITY>; 448 status = "disabled"; 449 }; 450 451 ecb030: ecb@3b000 { 452 compatible = "nordic,nrf-ecb"; 453 reg = <0x3b000 0x1000>; 454 interrupts = <59 NRF_DEFAULT_IRQ_PRIORITY>; 455 status = "disabled"; 456 }; 457 458 ccm031: ccm@3c000 { 459 compatible = "nordic,nrf-ccm"; 460 reg = <0x3c000 0x1000>; 461 interrupts = <60 NRF_DEFAULT_IRQ_PRIORITY>; 462 status = "disabled"; 463 }; 464 465 ecb031: ecb@3d000 { 466 compatible = "nordic,nrf-ecb"; 467 reg = <0x3d000 0x1000>; 468 status = "disabled"; 469 interrupts = <61 NRF_DEFAULT_IRQ_PRIORITY>; 470 }; 471 }; 472 473 tdd_peripherals: peripheral@bf000000 { 474 #address-cells = <1>; 475 #size-cells = <1>; 476 reg = <0xbf000000 0x1000000>; 477 ranges = <0x0 0xbf000000 0x1000000>; 478 479 tbm: tbm@3000 { 480 compatible = "nordic,nrf-tbm"; 481 reg = <0x3000 0x408>; 482 status = "disabled"; 483 interrupts = <127 NRF_DEFAULT_IRQ_PRIORITY>; 484 }; 485 486 tddconf: tddconf@1000 { 487 compatible = "nordic,nrf-tddconf"; 488 reg = <0x1000 0x10>; 489 status = "disabled"; 490 }; 491 }; 492 493 global_peripherals: peripheral@5f000000 { 494 #address-cells = <1>; 495 #size-cells = <1>; 496 reg = <0x5f000000 0x1000000>; 497 ranges = <0x0 0x5f000000 0x1000000>; 498 499 usbhs: usbhs@86000 { 500 compatible = "nordic,nrf-usbhs", "snps,dwc2"; 501 reg = <0x86000 0x1000>, <0x2f700000 0x40000>; 502 reg-names = "wrapper", "core"; 503 interrupts = <134 NRF_DEFAULT_IRQ_PRIORITY>; 504 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 505 num-in-eps = <8>; 506 num-out-eps = <10>; 507 ghwcfg1 = <0xaa555000>; 508 ghwcfg2 = <0x22abfc72>; 509 ghwcfg4 = <0x1e10aa60>; 510 status = "disabled"; 511 }; 512 513 exmif: exmif@95000 { 514 compatible = "nordic,nrf-exmif", "snps,designware-ssi"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <0x95000 0x500 0x95500 0xb00>; 518 reg-names = "wrapper", "core"; 519 interrupts = <149 NRF_DEFAULT_IRQ_PRIORITY>; 520 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 521 clock-frequency = <DT_FREQ_M(400)>; 522 fifo-depth = <32>; 523 status = "disabled"; 524 }; 525 526 cpusec_bellboard: mailbox@99000 { 527 reg = <0x99000 0x1000>; 528 status = "disabled"; 529 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 530 #mbox-cells = <1>; 531 }; 532 533 cpuapp_bellboard: mailbox@9a000 { 534 reg = <0x9a000 0x1000>; 535 status = "disabled"; 536 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 537 #mbox-cells = <1>; 538 }; 539 540 cpurad_bellboard: mailbox@9b000 { 541 reg = <0x9b000 0x1000>; 542 status = "disabled"; 543 power-domains = <&gpd NRF_GPD_FAST_ACTIVE0>; 544 #mbox-cells = <1>; 545 }; 546 547 canpll: clock-controller@8c2000{ 548 compatible = "nordic,nrf-auxpll"; 549 reg = <0x8c2000 0x1000>; 550 interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; 551 clocks = <&hfxo>; 552 #clock-cells = <0>; 553 nordic,ficrs = <&ficr NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE>; 554 nordic,frequency = <0>; 555 nordic,out-div = <2>; 556 nordic,out-drive = <0>; 557 nordic,current-tune = <6>; 558 nordic,sdm-disable; 559 nordic,range = "high"; 560 status = "disabled"; 561 }; 562 563 cpusys_vevif_tx: mailbox@8c8000 { 564 compatible = "nordic,nrf-vevif-task-tx"; 565 reg = <0x8c8000 0x1000>; 566 status = "disabled"; 567 #mbox-cells = <1>; 568 nordic,tasks = <32>; 569 nordic,tasks-mask = <0xfffff0ff>; 570 }; 571 572 ipct120: ipct@8d1000 { 573 compatible = "nordic,nrf-ipct-global"; 574 reg = <0x8d1000 0x1000>; 575 status = "disabled"; 576 channels = <8>; 577 global-domain-id = <12>; 578 }; 579 580 cpuflpr_vpr: vpr@8d4000 { 581 compatible = "nordic,nrf-vpr-coprocessor"; 582 reg = <0x8d4000 0x1000>; 583 status = "disabled"; 584 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 ranges = <0x0 0x8d4000 0x1000>; 588 589 cpuflpr_vevif_tx: mailbox@0 { 590 compatible = "nordic,nrf-vevif-task-tx"; 591 reg = <0x0 0x1000>; 592 status = "disabled"; 593 #mbox-cells = <1>; 594 nordic,tasks = <32>; 595 nordic,tasks-mask = <0xffff0000>; 596 }; 597 }; 598 599 can120: can@8d8000 { 600 compatible = "nordic,nrf-can"; 601 reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>; 602 reg-names = "wrapper", "m_can", "message_ram"; 603 interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>; 604 clocks = <&canpll>, <&hsfll120>; 605 clock-names = "auxpll", "hsfll"; 606 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 607 bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>; 608 status = "disabled"; 609 }; 610 611 dppic120: dppic@8e1000 { 612 compatible = "nordic,nrf-dppic-global"; 613 reg = <0x8e1000 0x1000>; 614 status = "disabled"; 615 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 616 }; 617 618 timer120: timer@8e2000 { 619 compatible = "nordic,nrf-timer"; 620 reg = <0x8e2000 0x1000>; 621 status = "disabled"; 622 cc-num = <6>; 623 interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>; 624 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 625 max-bit-width = <32>; 626 clocks = <&hsfll120>; 627 prescaler = <0>; 628 }; 629 630 timer121: timer@8e3000 { 631 compatible = "nordic,nrf-timer"; 632 reg = <0x8e3000 0x1000>; 633 status = "disabled"; 634 cc-num = <6>; 635 interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>; 636 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 637 max-bit-width = <32>; 638 clocks = <&hsfll120>; 639 prescaler = <0>; 640 }; 641 642 pwm120: pwm@8e4000 { 643 compatible = "nordic,nrf-pwm"; 644 reg = <0x8e4000 0x1000>; 645 status = "disabled"; 646 interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>; 647 clocks = <&hsfll120>; 648 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 649 #pwm-cells = <3>; 650 }; 651 652 spi120: spi@8e6000 { 653 compatible = "nordic,nrf-spim"; 654 reg = <0x8e6000 0x1000>; 655 status = "disabled"; 656 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 657 easydma-maxcnt-bits = <15>; 658 interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; 659 clocks = <&hsfll120>; 660 max-frequency = <DT_FREQ_M(32)>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 rx-delay-supported; 664 rx-delay = <1>; 665 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, 666 <NRF_FUN_SPIS_SCK>; 667 }; 668 669 uart120: uart@8e6000 { 670 compatible = "nordic,nrf-uarte"; 671 reg = <0x8e6000 0x1000>; 672 status = "disabled"; 673 interrupts = <230 NRF_DEFAULT_IRQ_PRIORITY>; 674 clocks = <&hsfll120>; 675 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 676 endtx-stoptx-supported; 677 frame-timeout-supported; 678 }; 679 680 spi121: spi@8e7000 { 681 compatible = "nordic,nrf-spim"; 682 reg = <0x8e7000 0x1000>; 683 status = "disabled"; 684 easydma-maxcnt-bits = <15>; 685 interrupts = <231 NRF_DEFAULT_IRQ_PRIORITY>; 686 clocks = <&hsfll120>; 687 power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>; 688 max-frequency = <DT_FREQ_M(32)>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 rx-delay-supported; 692 rx-delay = <1>; 693 nordic,clockpin-enable = <NRF_FUN_SPIM_SCK>, 694 <NRF_FUN_SPIS_SCK>; 695 }; 696 697 cpuppr_vpr: vpr@908000 { 698 compatible = "nordic,nrf-vpr-coprocessor"; 699 reg = <0x908000 0x1000>; 700 status = "disabled"; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 ranges = <0x0 0x908000 0x1000>; 704 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 705 706 cpuppr_vevif_tx: mailbox@0 { 707 compatible = "nordic,nrf-vevif-task-tx"; 708 reg = <0x0 0x1000>; 709 status = "disabled"; 710 #mbox-cells = <1>; 711 nordic,tasks = <16>; 712 nordic,tasks-mask = <0xfffffff0>; 713 }; 714 }; 715 716 ipct130: ipct@921000 { 717 compatible = "nordic,nrf-ipct-global"; 718 reg = <0x921000 0x1000>; 719 status = "disabled"; 720 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 721 channels = <8>; 722 global-domain-id = <13>; 723 }; 724 725 dppic130: dppic@922000 { 726 compatible = "nordic,nrf-dppic-global"; 727 reg = <0x922000 0x1000>; 728 status = "disabled"; 729 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 730 }; 731 732 rtc130: rtc@928000 { 733 compatible = "nordic,nrf-rtc"; 734 reg = <0x928000 0x1000>; 735 status = "disabled"; 736 cc-num = <4>; 737 clock-frequency = <32768>; 738 interrupts = <296 NRF_DEFAULT_IRQ_PRIORITY>; 739 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 740 clocks = <&lfclk>; 741 prescaler = <1>; 742 }; 743 744 rtc131: rtc@929000 { 745 compatible = "nordic,nrf-rtc"; 746 reg = <0x929000 0x1000>; 747 status = "disabled"; 748 cc-num = <4>; 749 clock-frequency = <32768>; 750 interrupts = <297 NRF_DEFAULT_IRQ_PRIORITY>; 751 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 752 clocks = <&lfclk>; 753 prescaler = <1>; 754 }; 755 756 wdt131: watchdog@92b000 { 757 compatible = "nordic,nrf-wdt"; 758 reg = <0x92b000 0x1000>; 759 status = "disabled"; 760 interrupts = <299 NRF_DEFAULT_IRQ_PRIORITY>; 761 clocks = <&lfclk>; 762 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 763 }; 764 765 wdt132: watchdog@92c000 { 766 compatible = "nordic,nrf-wdt"; 767 reg = <0x92c000 0x1000>; 768 status = "disabled"; 769 interrupts = <300 NRF_DEFAULT_IRQ_PRIORITY>; 770 clocks = <&lfclk>; 771 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 772 }; 773 774 egu130: egu@92d000 { 775 compatible = "nordic,nrf-egu"; 776 reg = <0x92d000 0x1000>; 777 status = "disabled"; 778 interrupts = <301 NRF_DEFAULT_IRQ_PRIORITY>; 779 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 780 }; 781 782 gpiote130: gpiote@934000 { 783 compatible = "nordic,nrf-gpiote"; 784 reg = <0x934000 0x1000>; 785 status = "disabled"; 786 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 787 instance = <130>; 788 }; 789 790 gpio0: gpio@938000 { 791 compatible = "nordic,nrf-gpio"; 792 reg = <0x938000 0x200>; 793 status = "disabled"; 794 #gpio-cells = <2>; 795 gpio-controller; 796 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 797 gpiote-instance = <&gpiote130>; 798 ngpios = <12>; 799 port = <0>; 800 }; 801 802 gpio1: gpio@938200 { 803 compatible = "nordic,nrf-gpio"; 804 reg = <0x938200 0x200>; 805 status = "disabled"; 806 #gpio-cells = <2>; 807 gpio-controller; 808 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 809 gpiote-instance = <&gpiote130>; 810 ngpios = <12>; 811 port = <1>; 812 }; 813 814 gpio2: gpio@938400 { 815 compatible = "nordic,nrf-gpio"; 816 reg = <0x938400 0x200>; 817 status = "disabled"; 818 #gpio-cells = <2>; 819 gpio-controller; 820 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 821 gpiote-instance = <&gpiote130>; 822 ngpios = <12>; 823 port = <2>; 824 }; 825 826 gpio6: gpio@938c00 { 827 compatible = "nordic,nrf-gpio"; 828 reg = <0x938c00 0x200>; 829 status = "disabled"; 830 #gpio-cells = <2>; 831 gpio-controller; 832 power-domains = <&gpd NRF_GPD_SLOW_MAIN>, 833 <&gpd NRF_GPD_FAST_ACTIVE1>; 834 power-domain-names = "peripheral", "pad"; 835 ngpios = <14>; 836 port = <6>; 837 }; 838 839 gpio7: gpio@938e00 { 840 compatible = "nordic,nrf-gpio"; 841 reg = <0x938e00 0x200>; 842 status = "disabled"; 843 #gpio-cells = <2>; 844 gpio-controller; 845 power-domains = <&gpd NRF_GPD_SLOW_MAIN>, 846 <&gpd NRF_GPD_FAST_ACTIVE1>; 847 power-domain-names = "peripheral", "pad"; 848 ngpios = <8>; 849 port = <7>; 850 }; 851 852 gpio9: gpio@939200 { 853 compatible = "nordic,nrf-gpio"; 854 reg = <0x939200 0x200>; 855 status = "disabled"; 856 #gpio-cells = <2>; 857 gpio-controller; 858 power-domains = <&gpd NRF_GPD_SLOW_MAIN>; 859 gpiote-instance = <&gpiote130>; 860 ngpios = <6>; 861 port = <9>; 862 }; 863 864 dppic131: dppic@981000 { 865 compatible = "nordic,nrf-dppic-global"; 866 reg = <0x981000 0x1000>; 867 status = "disabled"; 868 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 869 }; 870 871 adc: adc@982000 { 872 compatible = "nordic,nrf-saadc"; 873 reg = <0x982000 0x1000>; 874 interrupts = <386 NRF_DEFAULT_IRQ_PRIORITY>; 875 status = "disabled"; 876 #io-channel-cells = <1>; 877 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 878 zephyr,pm-device-runtime-auto; 879 }; 880 881 comp: comparator@983000 { 882 /* 883 * Use compatible "nordic,nrf-comp" to configure as COMP 884 * Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP 885 */ 886 compatible = "nordic,nrf-comp"; 887 reg = <0x983000 0x1000>; 888 status = "disabled"; 889 interrupts = <387 NRF_DEFAULT_IRQ_PRIORITY>; 890 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 891 }; 892 893 temp: temperature-sensor@984000 { 894 compatible = "nordic,nrf-temp"; 895 reg = <0x984000 0x1000>; 896 interrupts = <388 NRF_DEFAULT_IRQ_PRIORITY>; 897 status = "disabled"; 898 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 899 }; 900 901 nfct: nfct@985000 { 902 compatible = "nordic,nrf-nfct"; 903 reg = <0x985000 0x1000>; 904 status = "disabled"; 905 interrupts = <389 NRF_DEFAULT_IRQ_PRIORITY>; 906 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 907 }; 908 909 dppic132: dppic@991000 { 910 compatible = "nordic,nrf-dppic-global"; 911 reg = <0x991000 0x1000>; 912 status = "disabled"; 913 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 914 }; 915 916 pdm0: pdm@993000 { 917 compatible = "nordic,nrf-pdm"; 918 reg = <0x993000 0x1000>; 919 status = "disabled"; 920 interrupts = <403 NRF_DEFAULT_IRQ_PRIORITY>; 921 nordic,clockpin-enable = <NRF_FUN_PDM_CLK>; 922 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 923 }; 924 925 qdec130: qdec@994000 { 926 compatible = "nordic,nrf-qdec"; 927 reg = <0x994000 0x1000>; 928 status = "disabled"; 929 interrupts = <404 NRF_DEFAULT_IRQ_PRIORITY>; 930 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 931 }; 932 933 qdec131: qdec@995000 { 934 compatible = "nordic,nrf-qdec"; 935 reg = <0x995000 0x1000>; 936 status = "disabled"; 937 interrupts = <405 NRF_DEFAULT_IRQ_PRIORITY>; 938 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 939 }; 940 941 grtc: grtc@99c000 { 942 compatible = "nordic,nrf-grtc"; 943 reg = <0x99c000 0x1000>; 944 status = "disabled"; 945 cc-num = <16>; 946 clocks = <&lfclk>, <&fll16m>; 947 clock-names = "lfclock", "hfclock"; 948 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 949 }; 950 951 dppic133: dppic@9a1000 { 952 compatible = "nordic,nrf-dppic-global"; 953 reg = <0x9a1000 0x1000>; 954 status = "disabled"; 955 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 956 }; 957 958 timer130: timer@9a2000 { 959 compatible = "nordic,nrf-timer"; 960 reg = <0x9a2000 0x1000>; 961 status = "disabled"; 962 cc-num = <6>; 963 interrupts = <418 NRF_DEFAULT_IRQ_PRIORITY>; 964 clocks = <&fll16m>; 965 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 966 max-bit-width = <32>; 967 prescaler = <0>; 968 }; 969 970 timer131: timer@9a3000 { 971 compatible = "nordic,nrf-timer"; 972 reg = <0x9a3000 0x1000>; 973 status = "disabled"; 974 cc-num = <6>; 975 interrupts = <419 NRF_DEFAULT_IRQ_PRIORITY>; 976 clocks = <&fll16m>; 977 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 978 max-bit-width = <32>; 979 prescaler = <0>; 980 }; 981 982 pwm130: pwm@9a4000 { 983 compatible = "nordic,nrf-pwm"; 984 reg = <0x9a4000 0x1000>; 985 status = "disabled"; 986 interrupts = <420 NRF_DEFAULT_IRQ_PRIORITY>; 987 clocks = <&fll16m>; 988 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 989 #pwm-cells = <3>; 990 }; 991 992 i2c130: i2c@9a5000 { 993 compatible = "nordic,nrf-twim"; 994 reg = <0x9a5000 0x1000>; 995 status = "disabled"; 996 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 997 clocks = <&fll16m>; 998 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 999 easydma-maxcnt-bits = <15>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1003 <NRF_FUN_TWIM_SCL>; 1004 zephyr,pm-device-runtime-auto; 1005 }; 1006 1007 spi130: spi@9a5000 { 1008 compatible = "nordic,nrf-spim"; 1009 reg = <0x9a5000 0x1000>; 1010 status = "disabled"; 1011 easydma-maxcnt-bits = <15>; 1012 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 1013 clocks = <&fll16m>; 1014 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1015 max-frequency = <DT_FREQ_M(8)>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 rx-delay-supported; 1019 rx-delay = <1>; 1020 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1021 <NRF_FUN_SPIM_SCK>, 1022 <NRF_FUN_SPIS_MISO>, 1023 <NRF_FUN_SPIS_SCK>; 1024 }; 1025 1026 uart130: uart@9a5000 { 1027 compatible = "nordic,nrf-uarte"; 1028 reg = <0x9a5000 0x1000>; 1029 status = "disabled"; 1030 interrupts = <421 NRF_DEFAULT_IRQ_PRIORITY>; 1031 clocks = <&fll16m>; 1032 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1033 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1034 endtx-stoptx-supported; 1035 frame-timeout-supported; 1036 }; 1037 1038 i2c131: i2c@9a6000 { 1039 compatible = "nordic,nrf-twim"; 1040 reg = <0x9a6000 0x1000>; 1041 status = "disabled"; 1042 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 1043 clocks = <&fll16m>; 1044 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1045 easydma-maxcnt-bits = <15>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1049 <NRF_FUN_TWIM_SCL>; 1050 zephyr,pm-device-runtime-auto; 1051 }; 1052 1053 spi131: spi@9a6000 { 1054 compatible = "nordic,nrf-spim"; 1055 reg = <0x9a6000 0x1000>; 1056 status = "disabled"; 1057 easydma-maxcnt-bits = <15>; 1058 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 1059 clocks = <&fll16m>; 1060 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1061 max-frequency = <DT_FREQ_M(8)>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 rx-delay-supported; 1065 rx-delay = <1>; 1066 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1067 <NRF_FUN_SPIM_SCK>, 1068 <NRF_FUN_SPIS_MISO>, 1069 <NRF_FUN_SPIS_SCK>; 1070 }; 1071 1072 uart131: uart@9a6000 { 1073 compatible = "nordic,nrf-uarte"; 1074 reg = <0x9a6000 0x1000>; 1075 status = "disabled"; 1076 interrupts = <422 NRF_DEFAULT_IRQ_PRIORITY>; 1077 clocks = <&fll16m>; 1078 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1079 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1080 endtx-stoptx-supported; 1081 frame-timeout-supported; 1082 }; 1083 1084 dppic134: dppic@9b1000 { 1085 compatible = "nordic,nrf-dppic-global"; 1086 reg = <0x9b1000 0x1000>; 1087 status = "disabled"; 1088 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1089 }; 1090 1091 timer132: timer@9b2000 { 1092 compatible = "nordic,nrf-timer"; 1093 reg = <0x9b2000 0x1000>; 1094 status = "disabled"; 1095 cc-num = <6>; 1096 interrupts = <434 NRF_DEFAULT_IRQ_PRIORITY>; 1097 clocks = <&fll16m>; 1098 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1099 max-bit-width = <32>; 1100 prescaler = <0>; 1101 }; 1102 1103 timer133: timer@9b3000 { 1104 compatible = "nordic,nrf-timer"; 1105 reg = <0x9b3000 0x1000>; 1106 status = "disabled"; 1107 cc-num = <6>; 1108 interrupts = <435 NRF_DEFAULT_IRQ_PRIORITY>; 1109 clocks = <&fll16m>; 1110 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1111 max-bit-width = <32>; 1112 prescaler = <0>; 1113 }; 1114 1115 pwm131: pwm@9b4000 { 1116 compatible = "nordic,nrf-pwm"; 1117 reg = <0x9b4000 0x1000>; 1118 status = "disabled"; 1119 interrupts = <436 NRF_DEFAULT_IRQ_PRIORITY>; 1120 clocks = <&fll16m>; 1121 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1122 #pwm-cells = <3>; 1123 }; 1124 1125 i2c132: i2c@9b5000 { 1126 compatible = "nordic,nrf-twim"; 1127 reg = <0x9b5000 0x1000>; 1128 status = "disabled"; 1129 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 1130 clocks = <&fll16m>; 1131 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1132 easydma-maxcnt-bits = <15>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1136 <NRF_FUN_TWIM_SCL>; 1137 zephyr,pm-device-runtime-auto; 1138 }; 1139 1140 spi132: spi@9b5000 { 1141 compatible = "nordic,nrf-spim"; 1142 reg = <0x9b5000 0x1000>; 1143 status = "disabled"; 1144 easydma-maxcnt-bits = <15>; 1145 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 1146 clocks = <&fll16m>; 1147 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1148 max-frequency = <DT_FREQ_M(8)>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 rx-delay-supported; 1152 rx-delay = <1>; 1153 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1154 <NRF_FUN_SPIM_SCK>, 1155 <NRF_FUN_SPIS_MISO>, 1156 <NRF_FUN_SPIS_SCK>; 1157 }; 1158 1159 uart132: uart@9b5000 { 1160 compatible = "nordic,nrf-uarte"; 1161 reg = <0x9b5000 0x1000>; 1162 status = "disabled"; 1163 interrupts = <437 NRF_DEFAULT_IRQ_PRIORITY>; 1164 clocks = <&fll16m>; 1165 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1166 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1167 endtx-stoptx-supported; 1168 frame-timeout-supported; 1169 }; 1170 1171 i2c133: i2c@9b6000 { 1172 compatible = "nordic,nrf-twim"; 1173 reg = <0x9b6000 0x1000>; 1174 status = "disabled"; 1175 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 1176 clocks = <&fll16m>; 1177 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1178 easydma-maxcnt-bits = <15>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1182 <NRF_FUN_TWIM_SCL>; 1183 zephyr,pm-device-runtime-auto; 1184 }; 1185 1186 spi133: spi@9b6000 { 1187 compatible = "nordic,nrf-spim"; 1188 reg = <0x9b6000 0x1000>; 1189 status = "disabled"; 1190 easydma-maxcnt-bits = <15>; 1191 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 1192 clocks = <&fll16m>; 1193 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1194 max-frequency = <DT_FREQ_M(8)>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 rx-delay-supported; 1198 rx-delay = <1>; 1199 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1200 <NRF_FUN_SPIM_SCK>, 1201 <NRF_FUN_SPIS_MISO>, 1202 <NRF_FUN_SPIS_SCK>; 1203 }; 1204 1205 uart133: uart@9b6000 { 1206 compatible = "nordic,nrf-uarte"; 1207 reg = <0x9b6000 0x1000>; 1208 status = "disabled"; 1209 interrupts = <438 NRF_DEFAULT_IRQ_PRIORITY>; 1210 clocks = <&fll16m>; 1211 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1212 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1213 endtx-stoptx-supported; 1214 frame-timeout-supported; 1215 }; 1216 1217 dppic135: dppic@9c1000 { 1218 compatible = "nordic,nrf-dppic-global"; 1219 reg = <0x9c1000 0x1000>; 1220 status = "disabled"; 1221 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1222 }; 1223 1224 timer134: timer@9c2000 { 1225 compatible = "nordic,nrf-timer"; 1226 reg = <0x9c2000 0x1000>; 1227 status = "disabled"; 1228 cc-num = <6>; 1229 interrupts = <450 NRF_DEFAULT_IRQ_PRIORITY>; 1230 clocks = <&fll16m>; 1231 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1232 max-bit-width = <32>; 1233 prescaler = <0>; 1234 }; 1235 1236 timer135: timer@9c3000 { 1237 compatible = "nordic,nrf-timer"; 1238 reg = <0x9c3000 0x1000>; 1239 status = "disabled"; 1240 cc-num = <6>; 1241 interrupts = <451 NRF_DEFAULT_IRQ_PRIORITY>; 1242 clocks = <&fll16m>; 1243 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1244 max-bit-width = <32>; 1245 prescaler = <0>; 1246 }; 1247 1248 pwm132: pwm@9c4000 { 1249 compatible = "nordic,nrf-pwm"; 1250 reg = <0x9c4000 0x1000>; 1251 status = "disabled"; 1252 interrupts = <452 NRF_DEFAULT_IRQ_PRIORITY>; 1253 clocks = <&fll16m>; 1254 #pwm-cells = <3>; 1255 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1256 }; 1257 1258 i2c134: i2c@9c5000 { 1259 compatible = "nordic,nrf-twim"; 1260 reg = <0x9c5000 0x1000>; 1261 status = "disabled"; 1262 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1263 clocks = <&fll16m>; 1264 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1265 easydma-maxcnt-bits = <15>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1269 <NRF_FUN_TWIM_SCL>; 1270 zephyr,pm-device-runtime-auto; 1271 }; 1272 1273 spi134: spi@9c5000 { 1274 compatible = "nordic,nrf-spim"; 1275 reg = <0x9c5000 0x1000>; 1276 status = "disabled"; 1277 easydma-maxcnt-bits = <15>; 1278 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1279 clocks = <&fll16m>; 1280 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1281 max-frequency = <DT_FREQ_M(8)>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 rx-delay-supported; 1285 rx-delay = <1>; 1286 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1287 <NRF_FUN_SPIM_SCK>, 1288 <NRF_FUN_SPIS_MISO>, 1289 <NRF_FUN_SPIS_SCK>; 1290 }; 1291 1292 uart134: uart@9c5000 { 1293 compatible = "nordic,nrf-uarte"; 1294 reg = <0x9c5000 0x1000>; 1295 status = "disabled"; 1296 interrupts = <453 NRF_DEFAULT_IRQ_PRIORITY>; 1297 clocks = <&fll16m>; 1298 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1299 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1300 endtx-stoptx-supported; 1301 frame-timeout-supported; 1302 }; 1303 1304 i2c135: i2c@9c6000 { 1305 compatible = "nordic,nrf-twim"; 1306 reg = <0x9c6000 0x1000>; 1307 status = "disabled"; 1308 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1309 clocks = <&fll16m>; 1310 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1311 easydma-maxcnt-bits = <15>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1315 <NRF_FUN_TWIM_SCL>; 1316 zephyr,pm-device-runtime-auto; 1317 }; 1318 1319 spi135: spi@9c6000 { 1320 compatible = "nordic,nrf-spim"; 1321 reg = <0x9c6000 0x1000>; 1322 status = "disabled"; 1323 easydma-maxcnt-bits = <15>; 1324 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1325 clocks = <&fll16m>; 1326 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1327 max-frequency = <DT_FREQ_M(8)>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 rx-delay-supported; 1331 rx-delay = <1>; 1332 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1333 <NRF_FUN_SPIM_SCK>, 1334 <NRF_FUN_SPIS_MISO>, 1335 <NRF_FUN_SPIS_SCK>; 1336 }; 1337 1338 uart135: uart@9c6000 { 1339 compatible = "nordic,nrf-uarte"; 1340 reg = <0x9c6000 0x1000>; 1341 status = "disabled"; 1342 interrupts = <454 NRF_DEFAULT_IRQ_PRIORITY>; 1343 clocks = <&fll16m>; 1344 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1345 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1346 endtx-stoptx-supported; 1347 frame-timeout-supported; 1348 }; 1349 1350 dppic136: dppic@9d1000 { 1351 compatible = "nordic,nrf-dppic-global"; 1352 reg = <0x9d1000 0x1000>; 1353 status = "disabled"; 1354 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1355 }; 1356 1357 timer136: timer@9d2000 { 1358 compatible = "nordic,nrf-timer"; 1359 reg = <0x9d2000 0x1000>; 1360 status = "disabled"; 1361 cc-num = <6>; 1362 interrupts = <466 NRF_DEFAULT_IRQ_PRIORITY>; 1363 clocks = <&fll16m>; 1364 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1365 max-bit-width = <32>; 1366 prescaler = <0>; 1367 }; 1368 1369 timer137: timer@9d3000 { 1370 compatible = "nordic,nrf-timer"; 1371 reg = <0x9d3000 0x1000>; 1372 status = "disabled"; 1373 cc-num = <6>; 1374 interrupts = <467 NRF_DEFAULT_IRQ_PRIORITY>; 1375 clocks = <&fll16m>; 1376 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1377 max-bit-width = <32>; 1378 prescaler = <0>; 1379 }; 1380 1381 pwm133: pwm@9d4000 { 1382 compatible = "nordic,nrf-pwm"; 1383 reg = <0x9d4000 0x1000>; 1384 status = "disabled"; 1385 interrupts = <468 NRF_DEFAULT_IRQ_PRIORITY>; 1386 clocks = <&fll16m>; 1387 #pwm-cells = <3>; 1388 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1389 }; 1390 1391 i2c136: i2c@9d5000 { 1392 compatible = "nordic,nrf-twim"; 1393 reg = <0x9d5000 0x1000>; 1394 status = "disabled"; 1395 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1396 clocks = <&fll16m>; 1397 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1398 easydma-maxcnt-bits = <15>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1402 <NRF_FUN_TWIM_SCL>; 1403 zephyr,pm-device-runtime-auto; 1404 }; 1405 1406 spi136: spi@9d5000 { 1407 compatible = "nordic,nrf-spim"; 1408 reg = <0x9d5000 0x1000>; 1409 status = "disabled"; 1410 easydma-maxcnt-bits = <15>; 1411 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1412 clocks = <&fll16m>; 1413 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1414 max-frequency = <DT_FREQ_M(8)>; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 rx-delay-supported; 1418 rx-delay = <1>; 1419 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1420 <NRF_FUN_SPIM_SCK>, 1421 <NRF_FUN_SPIS_MISO>, 1422 <NRF_FUN_SPIS_SCK>; 1423 }; 1424 1425 uart136: uart@9d5000 { 1426 compatible = "nordic,nrf-uarte"; 1427 reg = <0x9d5000 0x1000>; 1428 status = "disabled"; 1429 interrupts = <469 NRF_DEFAULT_IRQ_PRIORITY>; 1430 clocks = <&fll16m>; 1431 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1432 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1433 endtx-stoptx-supported; 1434 frame-timeout-supported; 1435 }; 1436 1437 i2c137: i2c@9d6000 { 1438 compatible = "nordic,nrf-twim"; 1439 reg = <0x9d6000 0x1000>; 1440 status = "disabled"; 1441 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1442 clocks = <&fll16m>; 1443 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1444 easydma-maxcnt-bits = <15>; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 nordic,clockpin-enable = <NRF_FUN_TWIM_SDA>, 1448 <NRF_FUN_TWIM_SCL>; 1449 zephyr,pm-device-runtime-auto; 1450 }; 1451 1452 spi137: spi@9d6000 { 1453 compatible = "nordic,nrf-spim"; 1454 reg = <0x9d6000 0x1000>; 1455 status = "disabled"; 1456 easydma-maxcnt-bits = <15>; 1457 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1458 clocks = <&fll16m>; 1459 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1460 max-frequency = <DT_FREQ_M(8)>; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 rx-delay-supported; 1464 rx-delay = <1>; 1465 nordic,clockpin-enable = <NRF_FUN_SPIM_MOSI>, 1466 <NRF_FUN_SPIM_SCK>, 1467 <NRF_FUN_SPIS_MISO>, 1468 <NRF_FUN_SPIS_SCK>; 1469 }; 1470 1471 uart137: uart@9d6000 { 1472 compatible = "nordic,nrf-uarte"; 1473 reg = <0x9d6000 0x1000>; 1474 status = "disabled"; 1475 interrupts = <470 NRF_DEFAULT_IRQ_PRIORITY>; 1476 clocks = <&fll16m>; 1477 power-domains = <&gpd NRF_GPD_SLOW_ACTIVE>; 1478 nordic,clockpin-enable = <NRF_FUN_UART_TX>; 1479 endtx-stoptx-supported; 1480 frame-timeout-supported; 1481 }; 1482 }; 1483 }; 1484 1485 cpuapp_ppb: cpuapp-ppb-bus { 1486 #address-cells = <1>; 1487 #size-cells = <1>; 1488 1489 cpuapp_systick: timer@e000e010 { 1490 compatible = "arm,armv8m-systick"; 1491 reg = <0xe000e010 0x10>; 1492 status = "disabled"; 1493 }; 1494 1495 cpuapp_nvic: interrupt-controller@e000e100 { 1496 compatible = "arm,v8m-nvic"; 1497 reg = <0xe000e100 0xc00>; 1498 arm,num-irq-priority-bits = <3>; 1499 #interrupt-cells = <2>; 1500 interrupt-controller; 1501 #address-cells = <1>; 1502 }; 1503 }; 1504 1505 cpurad_ppb: cpurad-ppb-bus { 1506 #address-cells = <1>; 1507 #size-cells = <1>; 1508 1509 cpurad_systick: timer@e000e010 { 1510 compatible = "arm,armv8m-systick"; 1511 reg = <0xe000e010 0x10>; 1512 status = "disabled"; 1513 }; 1514 1515 cpurad_nvic: interrupt-controller@e000e100 { 1516 compatible = "arm,v8m-nvic"; 1517 reg = <0xe000e100 0xc00>; 1518 arm,num-irq-priority-bits = <3>; 1519 #interrupt-cells = <2>; 1520 interrupt-controller; 1521 #address-cells = <1>; 1522 }; 1523 }; 1524 1525 cpuppr_private: cpuppr-private-bus { 1526 #address-cells = <1>; 1527 #size-cells = <1>; 1528 1529 cpuppr_clic: interrupt-controller@f0000000 { 1530 compatible = "nordic,nrf-clic"; 1531 reg = <0xf0000000 0x3000>; 1532 status = "disabled"; 1533 #interrupt-cells = <2>; 1534 interrupt-controller; 1535 #address-cells = <1>; 1536 }; 1537 }; 1538 1539 cpuflpr_private: cpuflpr-private-bus { 1540 #address-cells = <1>; 1541 #size-cells = <1>; 1542 1543 cpuflpr_clic: interrupt-controller@f0000000 { 1544 compatible = "nordic,nrf-clic"; 1545 reg = <0xf0000000 0x3000>; 1546 status = "disabled"; 1547 #interrupt-cells = <2>; 1548 interrupt-controller; 1549 #address-cells = <1>; 1550 }; 1551 }; 1552 1553 temp_nrfs: temp { 1554 compatible = "nordic,nrf-temp-nrfs"; 1555 status = "disabled"; 1556 }; 1557}; 1558
