1 /*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_max32_i2c
8
9 #include <errno.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
13 #include <zephyr/irq.h>
14
15 #if defined(CONFIG_I2C_MAX32_DMA)
16 #include <zephyr/drivers/dma.h>
17 #endif /* CONFIG_I2C_MAX32_DMA */
18
19 #include <wrap_max32_i2c.h>
20
21 #define ADI_MAX32_I2C_INT_FL0_MASK 0x00FFFFFF
22 #define ADI_MAX32_I2C_INT_FL1_MASK 0x7
23
24 #define ADI_MAX32_I2C_STATUS_MASTER_BUSY BIT(5)
25
26 #define I2C_RECOVER_MAX_RETRIES 3
27
28 #ifdef CONFIG_I2C_MAX32_DMA
29 struct max32_i2c_dma_config {
30 const struct device *dev;
31 const uint32_t channel;
32 const uint32_t slot;
33 };
34 #endif /* CONFIG_I2C_MAX32_DMA */
35
36 /* Driver config */
37 struct max32_i2c_config {
38 mxc_i2c_regs_t *regs;
39 const struct pinctrl_dev_config *pctrl;
40 const struct device *clock;
41 struct max32_perclk perclk;
42 uint32_t bitrate;
43 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
44 uint8_t irqn;
45 void (*irq_config_func)(const struct device *dev);
46 #endif
47 #ifdef CONFIG_I2C_MAX32_DMA
48 struct max32_i2c_dma_config tx_dma;
49 struct max32_i2c_dma_config rx_dma;
50 #endif /* CONFIG_I2C_MAX32_DMA */
51 };
52
53 struct max32_i2c_data {
54 mxc_i2c_req_t req;
55 const struct device *dev;
56 struct k_sem lock;
57 uint8_t target_mode;
58 uint8_t flags;
59 #ifdef CONFIG_I2C_TARGET
60 struct i2c_target_config *target_cfg;
61 bool first_write;
62 #endif /* CONFIG_I2C_TARGET */
63 uint32_t readb;
64 uint32_t written;
65 #if defined(CONFIG_I2C_MAX32_INTERRUPT) || defined(CONFIG_I2C_MAX32_DMA)
66 struct k_sem xfer;
67 int err;
68 #endif
69 };
70
api_configure(const struct device * dev,uint32_t dev_cfg)71 static int api_configure(const struct device *dev, uint32_t dev_cfg)
72 {
73 int ret = 0;
74 const struct max32_i2c_config *const cfg = dev->config;
75 mxc_i2c_regs_t *i2c = cfg->regs;
76
77 switch (I2C_SPEED_GET(dev_cfg)) {
78 case I2C_SPEED_STANDARD: /** I2C Standard Speed: 100 kHz */
79 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE);
80 break;
81
82 case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */
83 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED);
84 break;
85
86 #if defined(MXC_I2C_FASTPLUS_SPEED)
87 case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */
88 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED);
89 break;
90 #endif
91
92 #if defined(MXC_I2C_HIGH_SPEED)
93 case I2C_SPEED_HIGH: /** I2C High Speed: 3.4 MHz */
94 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED);
95 break;
96 #endif
97
98 default:
99 /* Speed not supported */
100 return -ENOTSUP;
101 }
102
103 return ret;
104 }
105
106 #ifdef CONFIG_I2C_TARGET
api_target_register(const struct device * dev,struct i2c_target_config * cfg)107 static int api_target_register(const struct device *dev, struct i2c_target_config *cfg)
108 {
109 const struct max32_i2c_config *config = dev->config;
110 struct max32_i2c_data *data = dev->data;
111 mxc_i2c_regs_t *i2c = config->regs;
112 int ret;
113
114 data->target_cfg = cfg;
115
116 ret = MXC_I2C_Init(i2c, 0, cfg->address);
117 if (ret == E_NO_ERROR) {
118 data->target_mode = 1;
119 irq_enable(config->irqn);
120 MXC_I2C_SlaveTransactionAsync(i2c, NULL);
121 }
122
123 return ret == E_NO_ERROR ? 0 : E_FAIL;
124 }
125
api_target_unregister(const struct device * dev,struct i2c_target_config * cfg)126 static int api_target_unregister(const struct device *dev, struct i2c_target_config *cfg)
127 {
128 const struct max32_i2c_config *config = dev->config;
129 struct max32_i2c_data *data = dev->data;
130 mxc_i2c_regs_t *i2c = config->regs;
131
132 data->target_cfg = NULL;
133 data->target_mode = 0;
134
135 #ifndef CONFIG_I2C_MAX32_INTERRUPT
136 irq_disable(config->irqn);
137 #endif
138
139 return MXC_I2C_Init(i2c, 1, 0);
140 }
141
i2c_max32_target_callback(const struct device * dev,mxc_i2c_regs_t * i2c,mxc_i2c_slave_event_t event)142 static int i2c_max32_target_callback(const struct device *dev, mxc_i2c_regs_t *i2c,
143 mxc_i2c_slave_event_t event)
144 {
145 struct max32_i2c_data *data = dev->data;
146 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
147 static uint8_t rxval, txval, rxcnt;
148
149 switch (event) {
150 case MXC_I2C_EVT_MASTER_WR:
151 if (data->first_write && target_cb->write_requested) {
152 target_cb->write_requested(data->target_cfg);
153 data->first_write = false;
154 }
155 break;
156 case MXC_I2C_EVT_MASTER_RD:
157 break;
158 case MXC_I2C_EVT_RX_THRESH:
159 case MXC_I2C_EVT_OVERFLOW:
160 rxcnt = MXC_I2C_GetRXFIFOAvailable(i2c);
161 if (target_cb->write_received) {
162 while (rxcnt--) {
163 MXC_I2C_ReadRXFIFO(i2c, &rxval, 1);
164 target_cb->write_received(data->target_cfg, rxval);
165 }
166 } else {
167 MXC_I2C_ClearRXFIFO(i2c);
168 }
169 break;
170 case MXC_I2C_EVT_TX_THRESH:
171 case MXC_I2C_EVT_UNDERFLOW:
172 if (target_cb->read_requested) {
173 target_cb->read_requested(data->target_cfg, &txval);
174 MXC_I2C_WriteTXFIFO(i2c, &txval, 1);
175 }
176 if (target_cb->read_processed) {
177 target_cb->read_processed(data->target_cfg, &txval);
178 }
179 break;
180 case MXC_I2C_EVT_TRANS_COMP:
181 if (target_cb->stop) {
182 target_cb->stop(data->target_cfg);
183 }
184 data->first_write = true;
185 break;
186 }
187
188 return 0;
189 }
190 #endif /* CONFIG_I2C_TARGET */
191
api_recover_bus(const struct device * dev)192 static int api_recover_bus(const struct device *dev)
193 {
194 int ret;
195 const struct max32_i2c_config *const cfg = dev->config;
196 mxc_i2c_regs_t *i2c = cfg->regs;
197
198 ret = MXC_I2C_Recover(i2c, I2C_RECOVER_MAX_RETRIES);
199
200 return ret;
201 }
202
203 #ifndef CONFIG_I2C_MAX32_INTERRUPT
i2c_max32_transfer_sync(mxc_i2c_regs_t * i2c,struct max32_i2c_data * data)204 static int i2c_max32_transfer_sync(mxc_i2c_regs_t *i2c, struct max32_i2c_data *data)
205 {
206 uint32_t int_fl0, int_fl1;
207 uint32_t readb = 0;
208 mxc_i2c_req_t *req = &data->req;
209
210 /* Wait for acknowledge */
211 if (data->flags & (I2C_MSG_RESTART | I2C_MSG_READ)) {
212 do {
213 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
214 } while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) &&
215 !(int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR));
216 }
217
218 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
219 return -EIO;
220 }
221
222 while (req->tx_len > data->written) {
223 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
224 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD) {
225 data->written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[data->written],
226 req->tx_len - data->written);
227 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_TX_THD, 0);
228 }
229
230 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
231 return -EIO;
232 }
233 }
234
235 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0);
236 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
237 while (req->rx_len > readb) {
238 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
239 if (int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE)) {
240 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
241 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_RX_THD, 0);
242 }
243
244 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
245 return -EIO;
246 }
247
248 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
249 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) && (req->rx_len > readb) &&
250 MXC_I2C_GetRXFIFOAvailable(i2c) == 0) {
251 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
252 Wrap_MXC_I2C_Restart(i2c);
253 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_DONE, 0);
254 i2c->fifo = (req->addr << 1) | 0x1;
255 }
256 }
257
258 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
259 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
260 return -EIO;
261 }
262
263 if (data->flags & I2C_MSG_STOP) {
264 MXC_I2C_Stop(i2c);
265 do {
266 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
267 } while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_STOP));
268 }
269
270 if (req->rx_len) {
271 do {
272 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
273 } while (!(int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE));
274 } else {
275 while (Wrap_MXC_I2C_GetTxFIFOLevel(i2c) > 0) {
276 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
277 }
278 }
279 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
280
281 return 0;
282 }
283 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
284
285 #if defined(CONFIG_I2C_MAX32_DMA)
i2c_max32_dma_callback(const struct device * dev,void * arg,uint32_t channel,int status)286 static void i2c_max32_dma_callback(const struct device *dev, void *arg, uint32_t channel,
287 int status)
288 {
289 struct max32_i2c_data *data = arg;
290 const struct device *i2c_dev = data->dev;
291 const struct max32_i2c_config *const cfg = i2c_dev->config;
292
293 if (status < 0) {
294 data->err = -EIO;
295 Wrap_MXC_I2C_SetIntEn(cfg->regs, 0, 0);
296 k_sem_give(&data->xfer);
297 } else {
298 if (data->flags & I2C_MSG_STOP) {
299 Wrap_MXC_I2C_Stop(cfg->regs);
300 } else if (!(data->flags & I2C_MSG_READ)) {
301 MXC_I2C_EnableInt(cfg->regs, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
302 }
303 }
304 }
305
i2c_max32_tx_dma_load(const struct device * dev,struct i2c_msg * msg)306 static int i2c_max32_tx_dma_load(const struct device *dev, struct i2c_msg *msg)
307 {
308 int ret;
309 const struct max32_i2c_config *config = dev->config;
310 struct max32_i2c_data *data = dev->data;
311 struct dma_config dma_cfg = {0};
312 struct dma_block_config dma_blk = {0};
313
314 dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
315 dma_cfg.dma_callback = i2c_max32_dma_callback;
316 dma_cfg.user_data = (void *)data;
317 dma_cfg.dma_slot = config->tx_dma.slot;
318 dma_cfg.block_count = 1;
319 dma_cfg.source_data_size = 1U;
320 dma_cfg.source_burst_length = 1U;
321 dma_cfg.dest_data_size = 1U;
322 dma_cfg.head_block = &dma_blk;
323 dma_blk.block_size = msg->len;
324 dma_blk.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
325 dma_blk.source_address = (uint32_t)msg->buf;
326
327 ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg);
328 if (ret < 0) {
329 return ret;
330 }
331
332 return dma_start(config->tx_dma.dev, config->tx_dma.channel);
333 }
334
i2c_max32_rx_dma_load(const struct device * dev,struct i2c_msg * msg)335 static int i2c_max32_rx_dma_load(const struct device *dev, struct i2c_msg *msg)
336 {
337 int ret;
338 const struct max32_i2c_config *config = dev->config;
339 struct max32_i2c_data *data = dev->data;
340 struct dma_config dma_cfg = {0};
341 struct dma_block_config dma_blk = {0};
342
343 dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
344 dma_cfg.dma_callback = i2c_max32_dma_callback;
345 dma_cfg.user_data = (void *)data;
346 dma_cfg.dma_slot = config->rx_dma.slot;
347 dma_cfg.block_count = 1;
348 dma_cfg.source_data_size = 1U;
349 dma_cfg.source_burst_length = 1U;
350 dma_cfg.dest_data_size = 1U;
351 dma_cfg.head_block = &dma_blk;
352 dma_blk.block_size = msg->len;
353 dma_blk.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
354 dma_blk.dest_address = (uint32_t)msg->buf;
355
356 ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg);
357 if (ret < 0) {
358 return ret;
359 }
360
361 return dma_start(config->rx_dma.dev, config->rx_dma.channel);
362 }
363
i2c_max32_transfer_dma(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)364 static int i2c_max32_transfer_dma(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
365 uint16_t target_address)
366 {
367 int ret = 0;
368 const struct max32_i2c_config *const cfg = dev->config;
369 struct max32_i2c_data *data = dev->data;
370 mxc_i2c_regs_t *i2c = cfg->regs;
371 mxc_i2c_req_t *req = &data->req;
372 uint8_t target_rw;
373 unsigned int i = 0;
374
375 k_sem_take(&data->lock, K_FOREVER);
376
377 req->addr = target_address;
378 req->i2c = i2c;
379
380 MXC_I2C_SetRXThreshold(i2c, 1);
381 MXC_I2C_SetTXThreshold(i2c, 2);
382 MXC_I2C_ClearTXFIFO(i2c);
383 MXC_I2C_ClearRXFIFO(i2c);
384
385 /* First message should always begin with a START condition */
386 msgs[0].flags |= I2C_MSG_RESTART;
387
388 for (i = 0; i < num_msgs; i++) {
389 if (msgs[i].flags & I2C_MSG_READ) {
390 req->rx_len = msgs[i].len;
391 req->tx_len = 0;
392 target_rw = (target_address << 1) | 0x1;
393 ret = i2c_max32_rx_dma_load(dev, &msgs[i]);
394 if (ret < 0) {
395 break;
396 }
397 } else {
398 req->tx_len = msgs[i].len;
399 req->rx_len = 0;
400 target_rw = (target_address << 1) & ~0x1;
401 ret = i2c_max32_tx_dma_load(dev, &msgs[i]);
402 if (ret < 0) {
403 break;
404 }
405 }
406
407 /*
408 * If previous message ends with a STOP condition, this message
409 * should begin with a START
410 */
411 if (i > 0) {
412 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
413 msgs[i].flags |= I2C_MSG_RESTART;
414 }
415 }
416
417 data->flags = msgs[i].flags;
418 data->readb = 0;
419 data->written = 0;
420 data->err = 0;
421
422 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
423 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
424 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
425
426 if ((data->flags & I2C_MSG_RESTART)) {
427 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
428 MXC_I2C_Start(i2c);
429 Wrap_MXC_I2C_WaitForRestart(i2c);
430 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
431 } else if (req->tx_len) {
432 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
433 i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
434 }
435
436 ret = k_sem_take(&data->xfer, K_FOREVER);
437
438 i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN);
439 i2c->dma &= ~(ADI_MAX32_I2C_DMA_RX_EN);
440
441 if (data->err) {
442 ret = data->err;
443 }
444 if (ret) {
445 MXC_I2C_Stop(i2c);
446 dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel);
447 dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel);
448 break;
449 }
450 }
451
452 k_sem_give(&data->lock);
453
454 return ret;
455 }
456 #endif /* CONFIG_I2C_MAX32_DMA */
457
458 #ifdef CONFIG_I2C_MAX32_INTERRUPT
i2c_max32_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)459 static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
460 uint16_t target_address)
461 {
462 int ret = 0;
463 const struct max32_i2c_config *const cfg = dev->config;
464 struct max32_i2c_data *data = dev->data;
465 mxc_i2c_regs_t *i2c = cfg->regs;
466 mxc_i2c_req_t *req = &data->req;
467 uint8_t target_rw;
468 unsigned int i = 0;
469
470 req->i2c = i2c;
471 req->addr = target_address;
472
473 k_sem_take(&data->lock, K_FOREVER);
474
475 MXC_I2C_ClearRXFIFO(i2c);
476 MXC_I2C_ClearTXFIFO(i2c);
477 MXC_I2C_SetRXThreshold(i2c, 1);
478
479 /* First message should always begin with a START condition */
480 msgs[0].flags |= I2C_MSG_RESTART;
481
482 for (i = 0; i < num_msgs; i++) {
483 if (msgs[i].flags & I2C_MSG_READ) {
484 req->rx_buf = (unsigned char *)msgs[i].buf;
485 req->rx_len = msgs[i].len;
486 req->tx_buf = NULL;
487 req->tx_len = 0;
488 target_rw = (target_address << 1) | 0x1;
489 } else {
490 req->tx_buf = (unsigned char *)msgs[i].buf;
491 req->tx_len = msgs[i].len;
492 req->rx_buf = NULL;
493 req->rx_len = 0;
494 target_rw = (target_address << 1) & ~0x1;
495 }
496
497 /*
498 * If previous message ends with a STOP condition, this message
499 * should begin with a START
500 */
501 if (i > 0) {
502 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
503 msgs[i].flags |= I2C_MSG_RESTART;
504 }
505 }
506
507 data->flags = msgs[i].flags;
508 data->readb = 0;
509 data->written = 0;
510 data->err = 0;
511
512 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
513 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
514 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
515 if ((data->flags & I2C_MSG_RESTART)) {
516 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
517 MXC_I2C_Start(i2c);
518 Wrap_MXC_I2C_WaitForRestart(i2c);
519 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
520 } else {
521 if (req->tx_len) {
522 data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1);
523 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
524 } else {
525 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
526 }
527 }
528
529 ret = k_sem_take(&data->xfer, K_FOREVER);
530 if (data->err) {
531 MXC_I2C_Stop(i2c);
532 ret = data->err;
533 } else {
534 if (data->flags & I2C_MSG_STOP) {
535 /* Wait for busy flag to be cleared */
536 while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) {
537 }
538 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK,
539 ADI_MAX32_I2C_INT_FL1_MASK);
540 }
541 }
542 if (ret) {
543 break;
544 }
545 }
546
547 k_sem_give(&data->lock);
548
549 return ret;
550 }
551 #else
i2c_max32_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)552 static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
553 uint16_t target_address)
554 {
555 int ret = 0;
556 const struct max32_i2c_config *const cfg = dev->config;
557 struct max32_i2c_data *data = dev->data;
558 mxc_i2c_regs_t *i2c = cfg->regs;
559 mxc_i2c_req_t *req = &data->req;
560 uint8_t target_rw;
561 unsigned int i = 0;
562
563 req->i2c = i2c;
564 req->addr = target_address;
565
566 k_sem_take(&data->lock, K_FOREVER);
567
568 MXC_I2C_ClearRXFIFO(i2c);
569
570 /* First message should always begin with a START condition */
571 msgs[0].flags |= I2C_MSG_RESTART;
572
573 for (i = 0; i < num_msgs; i++) {
574 if (msgs[i].flags & I2C_MSG_READ) {
575 req->rx_buf = (unsigned char *)msgs[i].buf;
576 req->rx_len = msgs[i].len;
577 req->tx_buf = NULL;
578 req->tx_len = 0;
579 target_rw = (target_address << 1) | 0x1;
580 } else {
581 req->tx_buf = (unsigned char *)msgs[i].buf;
582 req->tx_len = msgs[i].len;
583 req->rx_buf = NULL;
584 req->rx_len = 0;
585 target_rw = (target_address << 1) & ~0x1;
586 }
587
588 /*
589 * If previous message ends with a STOP condition, this message
590 * should begin with a START
591 */
592 if (i > 0) {
593 if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
594 msgs[i].flags |= I2C_MSG_RESTART;
595 }
596 }
597
598 data->flags = msgs[i].flags;
599 data->readb = 0;
600 data->written = 0;
601
602 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
603
604 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
605 if (data->flags & I2C_MSG_RESTART) {
606 MXC_I2C_Start(i2c);
607 Wrap_MXC_I2C_WaitForRestart(i2c);
608 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
609 }
610 ret = i2c_max32_transfer_sync(i2c, data);
611 if (ret) {
612 MXC_I2C_Stop(i2c);
613 break;
614 }
615 }
616
617 k_sem_give(&data->lock);
618
619 return ret;
620 }
621 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
622
api_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t target_address)623 static int api_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
624 uint16_t target_address)
625 {
626 #if CONFIG_I2C_MAX32_DMA
627 const struct max32_i2c_config *cfg = dev->config;
628
629 if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
630 return i2c_max32_transfer_dma(dev, msgs, num_msgs, target_address);
631 }
632 #endif
633 return i2c_max32_transfer(dev, msgs, num_msgs, target_address);
634 }
635
636 #ifdef CONFIG_I2C_TARGET
i2c_max32_isr_target(const struct device * dev,mxc_i2c_regs_t * i2c)637 static void i2c_max32_isr_target(const struct device *dev, mxc_i2c_regs_t *i2c)
638 {
639 uint32_t ctrl;
640 uint32_t int_fl0;
641 uint32_t int_fl1;
642 uint32_t int_en0;
643 uint32_t int_en1;
644
645 ctrl = i2c->ctrl;
646 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
647 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
648 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
649
650 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
651 /* Error occurred, notify callback function and end transaction */
652 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
653
654 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
655 MXC_I2C_ClearTXFIFO(i2c);
656 MXC_I2C_ClearRXFIFO(i2c);
657 }
658
659 /* Check whether data is available if we received an interrupt occurred while receiving */
660 if (int_en0 & ADI_MAX32_I2C_INT_EN0_RX_THD || int_en1 & ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW) {
661 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_RX_THD) {
662 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_RX_THRESH);
663 }
664
665 if (int_fl1 & ADI_MAX32_I2C_INT_FL1_RX_OVERFLOW) {
666 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_OVERFLOW);
667 }
668 }
669
670 /* Check whether TX FIFO needs to be refilled if interrupt ocurred while transmitting */
671 if (int_en0 & (ADI_MAX32_I2C_INT_EN0_TX_THD | ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT) ||
672 int_en1 & ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW) {
673 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD) {
674 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TX_THRESH);
675 }
676
677 if (int_fl1 & ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW) {
678 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_UNDERFLOW);
679 }
680
681 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_LOCK_OUT) {
682 int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
683 int_en1 = 0;
684 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
685 }
686 }
687
688 /* Check if transaction completed or restart occurred */
689 if (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) {
690 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_STOP) {
691 /* Stop/NACK condition occurred, transaction complete */
692 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_TRANS_COMP);
693 int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
694 } else if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
695 /* Restart detected, re-arm address match interrupt */
696 int_en0 = ADI_MAX32_I2C_INT_EN0_ADDR_MATCH;
697 }
698 int_en1 = 0;
699 }
700
701 /* Check for address match interrupt */
702 if (int_en0 & ADI_MAX32_I2C_INT_EN0_ADDR_MATCH) {
703 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_MATCH) {
704 /* Address match occurred, prepare for transaction */
705 if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
706 /* Read request received from the master */
707 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_RD);
708 int_en0 = ADI_MAX32_I2C_INT_EN0_TX_THD |
709 ADI_MAX32_I2C_INT_EN0_TX_LOCK_OUT |
710 ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR;
711 int_en1 = ADI_MAX32_I2C_INT_EN1_TX_UNDERFLOW;
712 } else {
713 /* Write request received from the master */
714 i2c_max32_target_callback(dev, i2c, MXC_I2C_EVT_MASTER_WR);
715 int_en0 = ADI_MAX32_I2C_INT_EN0_RX_THD |
716 ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR;
717 int_en1 = ADI_MAX32_I2C_INT_EN1_RX_OVERFLOW;
718 }
719 }
720 }
721 Wrap_MXC_I2C_SetIntEn(i2c, int_en0, int_en1);
722 }
723 #endif /* CONFIG_I2C_TARGET */
724
725 #ifdef CONFIG_I2C_MAX32_INTERRUPT
i2c_max32_isr_controller(const struct device * dev,mxc_i2c_regs_t * i2c)726 static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c)
727 {
728 struct max32_i2c_data *data = dev->data;
729 mxc_i2c_req_t *req = &data->req;
730 uint32_t written, readb;
731 uint32_t txfifolevel;
732 uint32_t int_fl0, int_fl1;
733 uint32_t int_en0, int_en1;
734
735 written = data->written;
736 readb = data->readb;
737
738 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
739 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
740 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
741 txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c);
742
743 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
744 data->err = -EIO;
745 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
746 k_sem_give(&data->xfer);
747 return;
748 }
749
750 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK) {
751 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
752 if (written < req->tx_len) {
753 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
754 } else if (readb < req->rx_len) {
755 MXC_I2C_EnableInt(
756 i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0);
757 }
758 }
759
760 if (req->tx_len &&
761 (int_fl0 & (ADI_MAX32_I2C_INT_FL0_TX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
762 if (written < req->tx_len) {
763 written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written],
764 req->tx_len - written);
765 } else {
766 if (!(int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
767 /* We are done, stop sending more data */
768 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
769 if (data->flags & I2C_MSG_STOP) {
770 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
771 /* Done flag is not set if stop/restart is not set */
772 Wrap_MXC_I2C_Stop(i2c);
773 } else {
774 k_sem_give(&data->xfer);
775 }
776 }
777
778 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
779 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
780 k_sem_give(&data->xfer);
781 }
782 }
783 } else if ((int_fl0 & (ADI_MAX32_I2C_INT_FL0_RX_THD | ADI_MAX32_I2C_INT_FL0_DONE))) {
784 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb);
785 if (readb == req->rx_len) {
786 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0);
787 if (data->flags & I2C_MSG_STOP) {
788 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
789 Wrap_MXC_I2C_Stop(i2c);
790 k_sem_give(&data->xfer);
791 } else {
792 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE) {
793 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
794 k_sem_give(&data->xfer);
795 }
796 }
797 } else if ((int_en0 & ADI_MAX32_I2C_INT_EN0_DONE) &&
798 (int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
799 MXC_I2C_DisableInt(
800 i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE),
801 0);
802 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb);
803 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
804 i2c->fifo = (req->addr << 1) | 0x1;
805 Wrap_MXC_I2C_Restart(i2c);
806 }
807 }
808
809 data->written = written;
810 data->readb = readb;
811 }
812 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
813
814 #ifdef CONFIG_I2C_MAX32_DMA
i2c_max32_isr_controller_dma(const struct device * dev,mxc_i2c_regs_t * i2c)815 static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_t *i2c)
816 {
817 struct max32_i2c_data *data = dev->data;
818 const struct max32_i2c_config *cfg = dev->config;
819 struct dma_status dma_stat;
820 uint32_t int_fl0, int_fl1;
821 uint32_t int_en0, int_en1;
822
823 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1);
824 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1);
825 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
826
827 if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
828 data->err = -EIO;
829 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
830 k_sem_give(&data->xfer);
831 } else {
832 /* Run DMA once address is acknowledged */
833 if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK)) {
834 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
835 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
836 if (data->flags & I2C_MSG_READ) {
837 i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN;
838 } else {
839 i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
840 }
841 } else if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
842 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
843 if ((data->flags & I2C_MSG_READ)) {
844 dma_get_status(cfg->rx_dma.dev, cfg->rx_dma.channel, &dma_stat);
845 /* Send RESTART if more data is expected */
846 if (dma_stat.pending_length > 0) {
847 Wrap_MXC_I2C_SetRxCount(i2c, dma_stat.pending_length);
848 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
849 i2c->fifo = (data->req.addr << 1) | 0x1;
850 Wrap_MXC_I2C_Restart(i2c);
851 } else {
852 k_sem_give(&data->xfer);
853 }
854 } else {
855 k_sem_give(&data->xfer);
856 }
857 } else if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD)) {
858 MXC_I2C_DisableInt(
859 i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
860 k_sem_give(&data->xfer);
861 }
862 }
863 }
864 #endif /* CONFIG_I2C_MAX32_DMA */
865
866 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
i2c_max32_isr(const struct device * dev)867 static void i2c_max32_isr(const struct device *dev)
868 {
869 const struct max32_i2c_config *cfg = dev->config;
870 struct max32_i2c_data *data = dev->data;
871 mxc_i2c_regs_t *i2c = cfg->regs;
872
873 #ifdef CONFIG_I2C_MAX32_INTERRUPT
874 if (data->target_mode == 0) {
875 #ifdef CONFIG_I2C_MAX32_DMA
876 if ((cfg->tx_dma.channel != 0xFF) && (cfg->rx_dma.channel != 0xFF)) {
877 i2c_max32_isr_controller_dma(dev, i2c);
878 return;
879 }
880 #endif
881 i2c_max32_isr_controller(dev, i2c);
882 return;
883 }
884 #endif /* CONFIG_I2C_MAX32_INTERRUPT */
885
886 #ifdef CONFIG_I2C_TARGET
887 if (data->target_mode == 1) {
888 i2c_max32_isr_target(dev, i2c);
889 }
890 #endif
891 }
892 #endif /* CONFIG_I2C_TARGET || CONFIG_I2C_MAX32_INTERRUPT */
893
894 static DEVICE_API(i2c, api) = {
895 .configure = api_configure,
896 .transfer = api_transfer,
897 #ifdef CONFIG_I2C_TARGET
898 .target_register = api_target_register,
899 .target_unregister = api_target_unregister,
900 #endif
901 #ifdef CONFIG_I2C_RTIO
902 .iodev_submit = i2c_iodev_submit_fallback,
903 #endif
904 .recover_bus = api_recover_bus,
905 };
906
i2c_max32_init(const struct device * dev)907 static int i2c_max32_init(const struct device *dev)
908 {
909 const struct max32_i2c_config *const cfg = dev->config;
910 struct max32_i2c_data *data = dev->data;
911 mxc_i2c_regs_t *i2c = cfg->regs;
912 int ret = 0;
913
914 if (!device_is_ready(cfg->clock)) {
915 return -ENODEV;
916 }
917
918 MXC_I2C_Shutdown(i2c); /* Clear everything out */
919
920 ret = clock_control_on(cfg->clock, (clock_control_subsys_t)&cfg->perclk);
921 if (ret) {
922 return ret;
923 }
924
925 ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
926 if (ret) {
927 return ret;
928 }
929
930 ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */
931 if (ret) {
932 return ret;
933 }
934
935 MXC_I2C_SetFrequency(i2c, cfg->bitrate);
936
937 k_sem_init(&data->lock, 1, 1);
938
939 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
940 cfg->irq_config_func(dev);
941 #endif
942
943 #ifdef CONFIG_I2C_MAX32_INTERRUPT
944 irq_enable(cfg->irqn);
945
946 k_sem_init(&data->xfer, 0, 1);
947 #endif
948
949 #if defined(CONFIG_I2C_TARGET)
950 data->first_write = true;
951 data->target_mode = 0;
952 #endif
953 data->dev = dev;
954
955 return ret;
956 }
957
958 #if defined(CONFIG_I2C_TARGET) || defined(CONFIG_I2C_MAX32_INTERRUPT)
959 #define I2C_MAX32_CONFIG_IRQ_FUNC(n) \
960 .irq_config_func = i2c_max32_irq_config_func_##n, .irqn = DT_INST_IRQN(n),
961
962 #define I2C_MAX32_IRQ_CONFIG_FUNC(n) \
963 static void i2c_max32_irq_config_func_##n(const struct device *dev) \
964 { \
965 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_max32_isr, \
966 DEVICE_DT_INST_GET(n), 0); \
967 }
968 #else
969 #define I2C_MAX32_CONFIG_IRQ_FUNC(n)
970 #define I2C_MAX32_IRQ_CONFIG_FUNC(n)
971 #endif
972
973 #if CONFIG_I2C_MAX32_DMA
974 #define MAX32_DT_INST_DMA_CTLR(n, name) \
975 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
976 (DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, name))), (NULL))
977
978 #define MAX32_DT_INST_DMA_CELL(n, name, cell) \
979 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
980 (0xff))
981
982 #define MAX32_I2C_TX_DMA_INIT(n) \
983 .tx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, tx), \
984 .tx_dma.channel = MAX32_DT_INST_DMA_CELL(n, tx, channel), \
985 .tx_dma.slot = MAX32_DT_INST_DMA_CELL(n, tx, slot),
986 #define MAX32_I2C_RX_DMA_INIT(n) \
987 .rx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, rx), \
988 .rx_dma.channel = MAX32_DT_INST_DMA_CELL(n, rx, channel), \
989 .rx_dma.slot = MAX32_DT_INST_DMA_CELL(n, rx, slot),
990 #else
991 #define MAX32_I2C_TX_DMA_INIT(n)
992 #define MAX32_I2C_RX_DMA_INIT(n)
993 #endif
994
995 #define DEFINE_I2C_MAX32(_num) \
996 PINCTRL_DT_INST_DEFINE(_num); \
997 I2C_MAX32_IRQ_CONFIG_FUNC(_num) \
998 static const struct max32_i2c_config max32_i2c_dev_cfg_##_num = { \
999 .regs = (mxc_i2c_regs_t *)DT_INST_REG_ADDR(_num), \
1000 .pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
1001 .clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)), \
1002 .perclk.bus = DT_INST_CLOCKS_CELL(_num, offset), \
1003 .perclk.bit = DT_INST_CLOCKS_CELL(_num, bit), \
1004 .bitrate = DT_INST_PROP(_num, clock_frequency), \
1005 I2C_MAX32_CONFIG_IRQ_FUNC(_num) MAX32_I2C_TX_DMA_INIT(_num) \
1006 MAX32_I2C_RX_DMA_INIT(_num)}; \
1007 static struct max32_i2c_data max32_i2c_data_##_num; \
1008 I2C_DEVICE_DT_INST_DEFINE(_num, i2c_max32_init, NULL, &max32_i2c_data_##_num, \
1009 &max32_i2c_dev_cfg_##_num, PRE_KERNEL_2, \
1010 CONFIG_I2C_INIT_PRIORITY, &api);
1011
1012 DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_MAX32)
1013
