1/*
2 * Copyright (c) 2023 by Rivos Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	#address-cells = <0x01>;
9	#size-cells = <0x01>;
10	compatible = "lowrisc,opentitan-earlgrey";
11
12	cpus {
13		#address-cells = <0x01>;
14		#size-cells = <0x00>;
15
16		cpu@0 {
17			device_type = "cpu";
18			reg = <0x00>;
19			status = "okay";
20			compatible = "lowrisc,ibex", "riscv";
21			riscv,isa = "rv32imcb_zicsr_zifencei";
22
23			hlic: interrupt-controller {
24				#interrupt-cells = <0x01>;
25				interrupt-controller;
26				compatible = "riscv,cpu-intc";
27			};
28		};
29	};
30
31	soc {
32		#address-cells = <0x01>;
33		#size-cells = <0x01>;
34		compatible = "simple-bus";
35		ranges;
36
37		flash0: flash@20000000 {
38			reg = <0x20000000 0x100000>;
39			compatible = "soc-nv-flash";
40		};
41
42		ram0: memory@10000000 {
43			device_type = "memory";
44			reg = <0x10000000 0x10000>;
45		};
46
47		mtimer: timer@40100110 {
48			compatible = "riscv,machine-timer";
49			reg = <0x40100110 0x8 0x40100118 0x8>;
50			reg-names = "mtime", "mtimecmp";
51			interrupts-extended = <&hlic 7>;
52		};
53
54		aontimer: aontimer@40470000 {
55			compatible = "lowrisc,opentitan-aontimer";
56			reg = <0x40470000 0x1000>;
57			interrupts = <156 1>;
58			interrupt-names = "wdog_bark";
59			interrupt-parent = <&plic>;
60			clock-frequency = <200000>;
61			status = "disabled";
62		};
63
64		pwrmgr: pwrmgr@40400000 {
65			compatible = "lowrisc,opentitan-pwrmgr";
66			reg = <0x40400000 0x80>;
67			status = "okay";
68		};
69
70		plic: interrupt-controller@48000000 {
71			compatible = "sifive,plic-1.0.0";
72			#address-cells = <0>;
73			#interrupt-cells = <2>;
74			interrupt-controller;
75			interrupts-extended = <&hlic 11>;
76			reg = <0x48000000 0x04000000>;
77			riscv,max-priority = <7>;
78			riscv,ndev = <182>;
79			status = "okay";
80		};
81
82		uart0: serial@40000000{
83			reg = <0x40000000 0x1000>;
84			compatible = "lowrisc,opentitan-uart";
85			status = "disabled";
86		};
87
88		spi0: spi@40300000 {
89			compatible = "lowrisc,opentitan-spi";
90			status = "disabled";
91			reg = <0x40300000 0x100>;
92			clock-frequency = <96000000>;
93			#address-cells = <1>;
94			#size-cells = <0>;
95		};
96
97		spi1: spi@40310000 {
98			compatible = "lowrisc,opentitan-spi";
99			status = "disabled";
100			reg = <0x40310000 0x100>;
101			clock-frequency = <48000000>;
102			#address-cells = <1>;
103			#size-cells = <0>;
104		};
105	};
106};
107
108